ARM: arch timer: Set the TVAL before timer is enabled
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Message ID 1371846684-23730-1-git-send-email-rvaswani@codeaurora.org
State New, archived
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Series
  • ARM: arch timer: Set the TVAL before timer is enabled
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Commit Message

Rohit Vaswani June 21, 2013, 8:31 p.m. UTC
On some hardware, the timer deasserts the interrupt when a
new TVAL is written only when the enable bit is cleared.
Hence explicitly disable the timer and then program the
TVAL followed by enabling the timer.
If this order is not followed, there are chances that
you would not receive any timer interrupts.
This is done as suggested in https://lkml.org/lkml/2012/8/11/39

Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
---
 drivers/clocksource/arm_arch_timer.c |    5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)

Comments

Marc Zyngier June 24, 2013, 9:10 a.m. UTC | #1
On 21/06/13 21:31, Rohit Vaswani wrote:
> On some hardware, the timer deasserts the interrupt when a
> new TVAL is written only when the enable bit is cleared.
> Hence explicitly disable the timer and then program the
> TVAL followed by enabling the timer.
> If this order is not followed, there are chances that
> you would not receive any timer interrupts.
> This is done as suggested in https://lkml.org/lkml/2012/8/11/39
> 
> Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
> ---
>  drivers/clocksource/arm_arch_timer.c |    5 +++--
>  1 files changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
> index a2b2541..05ba0c2 100644
> --- a/drivers/clocksource/arm_arch_timer.c
> +++ b/drivers/clocksource/arm_arch_timer.c
> @@ -103,9 +103,10 @@ static inline void set_next_event(const int access, unsigned long evt)
>  {
>  	unsigned long ctrl;
>  	ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL);
> -	ctrl |= ARCH_TIMER_CTRL_ENABLE;
> -	ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
> +	ctrl &= ~(ARCH_TIMER_CTRL_ENABLE | ARCH_TIMER_CTRL_IT_MASK);
> +	arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl);
>  	arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt);
> +	ctrl |= ARCH_TIMER_CTRL_ENABLE;
>  	arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl);
>  }

Maybe that would deserve a comment in the code so people don't get the
idea it can be reordered to save the extra write?

Other than that, and FWIW:
Acked-by: Marc Zyngier <marc.zyngier@arm.com>

	M.

Patch
diff mbox series

diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index a2b2541..05ba0c2 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -103,9 +103,10 @@  static inline void set_next_event(const int access, unsigned long evt)
 {
 	unsigned long ctrl;
 	ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL);
-	ctrl |= ARCH_TIMER_CTRL_ENABLE;
-	ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
+	ctrl &= ~(ARCH_TIMER_CTRL_ENABLE | ARCH_TIMER_CTRL_IT_MASK);
+	arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl);
 	arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt);
+	ctrl |= ARCH_TIMER_CTRL_ENABLE;
 	arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl);
 }