From: Kever Yang <kever.yang@rock-chips.com>
To: Paul Zimmerman <paulz@synopsys.com>, heiko@sntech.de
Cc: dianders@chromium.org, olof@lixom.net, sonnyrao@chromium.org,
addy.ke@rock-chips.com, cf@rock-chips.com, xjq@rock-chips.com,
wulf@rock-chips.com, lyz@rock-chips.com, hj@rock-chips.com,
huangtao@rock-chips.com, Kever Yang <kever.yang@rock-chips.com>,
Rob Herring <robh+dt@kernel.org>, Pawel Moll <pawel.moll@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Ian Campbell <ijc+devicetree@hellion.org.uk>,
Kumar Gala <galak@codeaurora.org>,
Russell King <linux@arm.linux.org.uk>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: [REPOST PATCH v3 4/5] ARM: dts: Fix the sort ordering of EHCI and HSIC in rk3288.dtsi
Date: Thu, 31 Jul 2014 14:26:24 -0700 [thread overview]
Message-ID: <1406841985-15790-5-git-send-email-kever.yang@rock-chips.com> (raw)
In-Reply-To: <1406841985-15790-1-git-send-email-kever.yang@rock-chips.com>
From: Doug Anderson <dianders@chromium.org>
The EHCI and HSIC device tree nodes were added in the wrong place.
Fix them.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---
Changes in v3:
- EHCI and HSIC move new for version 3.
Changes in v2: None
arch/arm/boot/dts/rk3288.dtsi | 41 ++++++++++++++++++++---------------------
1 file changed, 20 insertions(+), 21 deletions(-)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index a5607a1..673dee3 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -205,6 +205,17 @@
status = "disabled";
};
+ usb_host0_ehci: ehci@ff500000 {
+ compatible = "generic-ehci";
+ reg = <0xff500000 0x100>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_USBHOST0>;
+ clock-names = "usbhost";
+ status = "disabled";
+ };
+
+ /* NOTE: ohci@ff520000 doesn't actually work on hardware */
+
usb_host1: usb@ff540000 {
compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
"snps,dwc2";
@@ -225,6 +236,15 @@
status = "disabled";
};
+ usb_hsic: ehci@ff5c0000 {
+ compatible = "generic-ehci";
+ reg = <0xff5c0000 0x100>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HSIC>;
+ clock-names = "usbhost";
+ status = "disabled";
+ };
+
uart2: serial@ff690000 {
compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
reg = <0xff690000 0x100>;
@@ -319,27 +339,6 @@
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
-
- usb_host0_ehci: ehci@ff500000 {
- compatible = "generic-ehci";
- reg = <0xff500000 0x100>;
- interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru HCLK_USBHOST0>;
- clock-names = "usbhost";
- status = "disabled";
- };
-
- /* NOTE: ohci@ff520000 doesn't actually work on hardware */
-
- usb_hsic: ehci@ff5c0000 {
- compatible = "generic-ehci";
- reg = <0xff5c0000 0x100>;
- interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru HCLK_HSIC>;
- clock-names = "usbhost";
- status = "disabled";
- };
-
gic: interrupt-controller@ffc01000 {
compatible = "arm,gic-400";
interrupt-controller;
--
1.7.9.5
next prev parent reply other threads:[~2014-07-31 21:26 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-07-31 21:26 [REPOST PATCH v3 0/5] Patches to add support for Rockchip dwc2 controller Kever Yang
2014-07-31 21:26 ` [REPOST PATCH v3 1/5] Documentation: dt-bindings: add dt binding info for Rockchip dwc2 Kever Yang
2014-07-31 21:26 ` [REPOST PATCH v3 2/5] usb: dwc2: add compatible data for rockchip soc Kever Yang
2014-07-31 21:26 ` [REPOST PATCH v3 3/5] ARM: dts: add rk3288 dwc2 controller support Kever Yang
2014-07-31 21:26 ` Kever Yang [this message]
2014-07-31 22:01 ` [REPOST PATCH v3 4/5] ARM: dts: Fix the sort ordering of EHCI and HSIC in rk3288.dtsi Doug Anderson
2014-07-31 21:26 ` [REPOST PATCH v3 5/5] ARM: dts: Enable USB otg and host1(dwc) on rk3288-evb Kever Yang
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