[PATCH v4 06/15] drm: bridge/dw_hdmi: adjust n/cts setting order

From: Yakir Yang <ykk@rock-chips.com>
To: djkurtz@chromium.org, dianders@chromium.org,
	linux-rockchip@lists.infradead.org
Cc: David Airlie <airlied@linux.ie>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Russell King <rmk+kernel@arm.linux.org.uk>,
	Yakir Yang <ykk@rock-chips.com>,
	Andy Yan <andy.yan@rock-chips.com>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Fabio Estevam <fabio.estevam@freescale.com>,
	dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org,
	mmind00@googlemail.com, marcheu@chromium.org,
	mark.yao@rock-chips.com
Subject: [PATCH v4 06/15] drm: bridge/dw_hdmi: adjust n/cts setting order
Date: Sat, 28 Feb 2015 21:40:30 -0500	[thread overview]
Message-ID: <1425177630-2024-1-git-send-email-ykk@rock-chips.com> (raw)
In-Reply-To: <1425175834-24661-1-git-send-email-ykk@rock-chips.com>

From: Daniel Kurtz <djkurtz@chromium.org>

This patch changes the order to:
- write CTS3 CTS_manual (if supported) | N_shift | CTS[19:16]
- write CTS2 CTS[15:8]
- write CTS1 CTS[7:0]
- write N3 N[19:16]
- write N2 N[15:8]
- write N1 N[7:0]

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
---
Changes in v4:
- Combine CTS3 registers setting, reduce register operate times

Changes in v3:
- Only adjust the n/cts setting order

Changes in v2: None

 drivers/gpu/drm/bridge/dw_hdmi.c | 25 +++++++++++++++----------
 drivers/gpu/drm/bridge/dw_hdmi.h |  6 ++++--
 2 files changed, 19 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/bridge/dw_hdmi.c b/drivers/gpu/drm/bridge/dw_hdmi.c
index 3d7c048..12d8b7e 100644
--- a/drivers/gpu/drm/bridge/dw_hdmi.c
+++ b/drivers/gpu/drm/bridge/dw_hdmi.c
@@ -199,19 +199,24 @@ static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
 static void hdmi_set_clock_regenerator(struct dw_hdmi *hdmi,
 				       unsigned int n, unsigned int cts)
 {
-	hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
-	hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
-	hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
+	u8 cts3 = 0;
 
-	/* nshift factor = 0 */
-	hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
-	/* Must be set/cleared first */
-	hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
+	/* set CTS_MANUAL (if present) */
+	if (hdmi->id.design == 0x20)
+		cts3 = HDMI_AUD_CTS3_CTS_MANUAL;
 
-	hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
+	cts3 |= HDMI_AUD_CTS3_N_SHIFT_1 << HDMI_AUD_CTS3_N_SHIFT_OFFSET;
+	cts3 |= (cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK;
+
+	/* write CTS values; CTS3 must be written first */
+	hdmi_writeb(hdmi, cts3, HDMI_AUD_CTS3);
 	hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
-	hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
-		    HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
+	hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
+
+	/* write N values; N1 must be written last */
+	hdmi_writeb(hdmi, (n >> 16) & 0xf, HDMI_AUD_N3);
+	hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
+	hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
 }
 
 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk,
diff --git a/drivers/gpu/drm/bridge/dw_hdmi.h b/drivers/gpu/drm/bridge/dw_hdmi.h
index e4ba634..c7ac538 100644
--- a/drivers/gpu/drm/bridge/dw_hdmi.h
+++ b/drivers/gpu/drm/bridge/dw_hdmi.h
@@ -916,8 +916,10 @@ enum {
 	HDMI_AUD_CTS3_N_SHIFT_64 = 0x60,
 	HDMI_AUD_CTS3_N_SHIFT_128 = 0x80,
 	HDMI_AUD_CTS3_N_SHIFT_256 = 0xa0,
-	/* note that the CTS3 MANUAL bit has been removed
-	   from our part. Can't set it, will read as 0. */
+	/*
+	 * Note: CTS_MANUAL is not present on iMX6 dw_hdmi, but is present on
+	 * rk3288 (design_id = 0x20).
+	 */
 	HDMI_AUD_CTS3_CTS_MANUAL = 0x10,
 	HDMI_AUD_CTS3_AUDCTS19_16_MASK = 0x0f,
 
-- 
2.1.2


