From: "Suzuki K. Poulose" <suzuki.poulose@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: Catalin.Marinas@arm.com, Will.Deacon@arm.com,
Mark.Rutland@arm.com, edward.nevill@linaro.org, aph@redhat.com,
linux-kernel@vger.kernel.org, andre.przywara@arm.com,
ard.biesheuvel@linaro.org, dave.martin@arm.com,
marc.zyngier@arm.com,
"Suzuki K. Poulose" <suzuki.poulose@arm.com>
Subject: [PATCH 16/22] arm64/debug: Make use of the system wide safe value
Date: Wed, 16 Sep 2015 15:21:14 +0100 [thread overview]
Message-ID: <1442413280-31885-17-git-send-email-suzuki.poulose@arm.com> (raw)
In-Reply-To: <1442413280-31885-1-git-send-email-suzuki.poulose@arm.com>
From: "Suzuki K. Poulose" <suzuki.poulose@arm.com>
Use the system wide value of ID_AA64DFR0 to make safer decisions
Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com>
---
arch/arm64/include/asm/hw_breakpoint.h | 14 ++------------
arch/arm64/kernel/debug-monitors.c | 6 ++++--
arch/arm64/kernel/hw_breakpoint.c | 19 ++++++++++++++++++-
3 files changed, 24 insertions(+), 15 deletions(-)
diff --git a/arch/arm64/include/asm/hw_breakpoint.h b/arch/arm64/include/asm/hw_breakpoint.h
index 4c47cb2..0251768 100644
--- a/arch/arm64/include/asm/hw_breakpoint.h
+++ b/arch/arm64/include/asm/hw_breakpoint.h
@@ -119,6 +119,8 @@ extern int arch_install_hw_breakpoint(struct perf_event *bp);
extern void arch_uninstall_hw_breakpoint(struct perf_event *bp);
extern void hw_breakpoint_pmu_read(struct perf_event *bp);
extern int hw_breakpoint_slots(int type);
+extern int get_num_brps(void);
+extern int get_num_wrps(void);
#ifdef CONFIG_HAVE_HW_BREAKPOINT
extern void hw_breakpoint_thread_switch(struct task_struct *next);
@@ -134,17 +136,5 @@ static inline void ptrace_hw_copy_thread(struct task_struct *task)
extern struct pmu perf_ops_bp;
-/* Determine number of BRP registers available. */
-static inline int get_num_brps(void)
-{
- return ((read_cpuid(ID_AA64DFR0_EL1) >> 12) & 0xf) + 1;
-}
-
-/* Determine number of WRP registers available. */
-static inline int get_num_wrps(void)
-{
- return ((read_cpuid(ID_AA64DFR0_EL1) >> 20) & 0xf) + 1;
-}
-
#endif /* __KERNEL__ */
#endif /* __ASM_BREAKPOINT_H */
diff --git a/arch/arm64/kernel/debug-monitors.c b/arch/arm64/kernel/debug-monitors.c
index 9b3b62a..9ca5f77 100644
--- a/arch/arm64/kernel/debug-monitors.c
+++ b/arch/arm64/kernel/debug-monitors.c
@@ -26,14 +26,16 @@
#include <linux/stat.h>
#include <linux/uaccess.h>
-#include <asm/debug-monitors.h>
+#include <asm/cpufeature.h>
#include <asm/cputype.h>
+#include <asm/debug-monitors.h>
#include <asm/system_misc.h>
/* Determine debug architecture. */
u8 debug_monitors_arch(void)
{
- return read_cpuid(ID_AA64DFR0_EL1) & 0xf;
+ return cpuid_feature_extract_field(read_system_reg(SYS_ID_AA64DFR0_EL1),
+ ID_AA64DFR0_DEBUGVER_SHIFT);
}
/*
diff --git a/arch/arm64/kernel/hw_breakpoint.c b/arch/arm64/kernel/hw_breakpoint.c
index c97040e..1fa0476 100644
--- a/arch/arm64/kernel/hw_breakpoint.c
+++ b/arch/arm64/kernel/hw_breakpoint.c
@@ -28,11 +28,12 @@
#include <linux/ptrace.h>
#include <linux/smp.h>
+#include <asm/cpufeature.h>
+#include <asm/cputype.h>
#include <asm/current.h>
#include <asm/debug-monitors.h>
#include <asm/hw_breakpoint.h>
#include <asm/traps.h>
-#include <asm/cputype.h>
#include <asm/system_misc.h>
/* Breakpoint currently in use for each BRP. */
@@ -48,6 +49,22 @@ static DEFINE_PER_CPU(int, stepping_kernel_bp);
static int core_num_brps;
static int core_num_wrps;
+/* Determine number of BRP registers available. */
+int get_num_brps(void)
+{
+ return 1 +
+ cpuid_feature_extract_field(read_system_reg(SYS_ID_AA64DFR0_EL1),
+ ID_AA64DFR0_BRPS_SHIFT);
+}
+
+/* Determine number of WRP registers available. */
+int get_num_wrps(void)
+{
+ return 1 +
+ cpuid_feature_extract_field(read_system_reg(SYS_ID_AA64DFR0_EL1),
+ ID_AA64DFR0_WRPS_SHIFT);
+}
+
int hw_breakpoint_slots(int type)
{
/*
--
1.7.9.5
next prev parent reply other threads:[~2015-09-16 14:24 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-16 14:20 [PATCH 00/22] arm64: Consolidate CPU feature handling Suzuki K. Poulose
2015-09-16 14:20 ` [PATCH 01/22] arm64: Make the CPU information more clear Suzuki K. Poulose
2015-09-16 14:21 ` [PATCH 02/22] arm64: Delay ELF HWCAP initialisation until all CPUs are up Suzuki K. Poulose
2015-09-16 14:21 ` [PATCH 03/22] arm64: Move cpu feature detection code Suzuki K. Poulose
2015-09-16 14:21 ` [PATCH 04/22] arm64: Move mixed endian support detection Suzuki K. Poulose
2015-09-16 14:21 ` [PATCH 05/22] arm64: Move /proc/cpuinfo handling code Suzuki K. Poulose
2015-09-16 14:21 ` [PATCH 06/22] arm64: sys_reg: Define System register encoding Suzuki K. Poulose
2015-09-16 14:21 ` [PATCH 07/22] arm64: Keep track of CPU feature registers Suzuki K. Poulose
2015-09-25 11:38 ` Dave Martin
2015-09-25 13:05 ` Suzuki K. Poulose
2015-09-16 14:21 ` [PATCH 08/22] arm64: Consolidate CPU Sanity check to CPU Feature infrastructure Suzuki K. Poulose
2015-09-16 14:21 ` [PATCH 09/22] arm64: Read system wide CPUID value Suzuki K. Poulose
2015-09-16 14:21 ` [PATCH 10/22] arm64: Cleanup mixed endian support detection Suzuki K. Poulose
2015-09-16 14:21 ` [PATCH 11/22] arm64: Populate cpuinfo after notify_cpu_starting Suzuki K. Poulose
2015-09-16 14:21 ` [PATCH 12/22] arm64: Delay cpu feature checks Suzuki K. Poulose
2015-09-16 14:21 ` [PATCH 13/22] arm64: Make use of system wide capability checks Suzuki K. Poulose
2015-09-16 14:21 ` [PATCH 14/22] arm64: Cleanup HWCAP handling Suzuki K. Poulose
2015-09-16 14:21 ` [PATCH 15/22] arm64: Move FP/ASIMD hwcap handling to common code Suzuki K. Poulose
2015-09-16 14:21 ` Suzuki K. Poulose [this message]
2015-09-29 12:17 ` [PATCH 16/22] arm64/debug: Make use of the system wide safe value Vladimir Murzin
2015-09-29 12:46 ` Suzuki K. Poulose
2015-09-30 16:13 ` Suzuki K. Poulose
2015-09-16 14:21 ` [PATCH 17/22] arm64/kvm: Make use of the system wide safe values Suzuki K. Poulose
2015-09-16 14:21 ` [PATCH 18/22] arm64: Add helper to decode register from instruction Suzuki K. Poulose
2015-09-16 14:21 ` [PATCH 19/22] arm64: cpufeature: Track the user visible fields Suzuki K. Poulose
2015-09-16 14:21 ` [PATCH 20/22] arm64: Expose feature registers by emulating MRS Suzuki K. Poulose
2015-09-16 14:21 ` [PATCH 21/22] arm64: cpuinfo: Expose MIDR_EL1 and REVIDR_EL1 to sysfs Suzuki K. Poulose
2015-09-16 14:21 ` [PATCH 22/22] arm64: feature registers: Documentation Suzuki K. Poulose
2015-09-18 9:23 ` [PATCH 00/22] arm64: Consolidate CPU feature handling Suzuki K. Poulose
2015-09-22 15:19 ` James Morse
2015-09-22 15:21 ` Suzuki K. Poulose
2015-09-23 15:56 ` Dave Martin
2015-09-23 15:58 ` Suzuki K. Poulose
2015-09-23 16:37 ` Suzuki K. Poulose
2015-09-23 17:08 ` Dave P Martin
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