From: Stephane Eranian <eranian@google.com>
To: linux-kernel@vger.kernel.org
Cc: acme@redhat.com, peterz@infradead.org, mingo@elte.hu,
ak@linux.intel.com, kan.liang@intel.com
Subject: [PATCH v3 1/4] perf/x86: fix LBR issues on Intel Atom
Date: Thu, 3 Dec 2015 23:33:17 +0100 [thread overview]
Message-ID: <1449182000-31524-2-git-send-email-eranian@google.com> (raw)
In-Reply-To: <1449182000-31524-1-git-send-email-eranian@google.com>
This patches fixes the LBR kernel crashes on Intel Atom.
The kernel was assuming that if the CPU supports 64-bit format
LBR, then it has an LBR_SELECT MSR. Atom uses 64-bit LBR format
but does not have LBR_SELECT. That was causing NULL pointer
dereferences in a couple of places.
Fixes: 96f3eda6 ("perf/x86/intel: Fix static checker warning in lbr enable")
Signed-off-by: Stephane Eranian <eranian@google.com>
---
arch/x86/kernel/cpu/perf_event_intel_lbr.c | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/arch/x86/kernel/cpu/perf_event_intel_lbr.c b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
index e2fad0c..1390148 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_lbr.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
@@ -161,7 +161,7 @@ static void __intel_pmu_lbr_enable(bool pmi)
*/
if (cpuc->lbr_sel)
lbr_select = cpuc->lbr_sel->config & x86_pmu.lbr_sel_mask;
- if (!pmi)
+ if (!pmi && cpuc->lbr_sel)
wrmsrl(MSR_LBR_SELECT, lbr_select);
rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
@@ -430,7 +430,7 @@ static void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc)
*/
static void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc)
{
- bool need_info = !(cpuc->lbr_sel->config & LBR_NO_INFO);
+ bool need_info = false;
unsigned long mask = x86_pmu.lbr_nr - 1;
int lbr_format = x86_pmu.intel_cap.lbr_format;
u64 tos = intel_pmu_lbr_tos();
@@ -438,8 +438,11 @@ static void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc)
int out = 0;
int num = x86_pmu.lbr_nr;
- if (cpuc->lbr_sel->config & LBR_CALL_STACK)
- num = tos;
+ if (cpuc->lbr_sel) {
+ need_info = !(cpuc->lbr_sel->config & LBR_NO_INFO);
+ if (cpuc->lbr_sel->config & LBR_CALL_STACK)
+ num = tos;
+ }
for (i = 0; i < num; i++) {
unsigned long lbr_idx = (tos - i) & mask;
--
1.9.1
next prev parent reply other threads:[~2015-12-03 22:34 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-12-03 22:33 [PATCH v3 0/2] perf/x86: fixes and improvements for Intel Atom PEBS/LBR support Stephane Eranian
2015-12-03 22:33 ` Stephane Eranian [this message]
2016-01-06 18:52 ` [tip:perf/core] perf/x86: Fix LBR related crashes on Intel Atom tip-bot for Stephane Eranian
2015-12-03 22:33 ` [PATCH v3 2/4] perf/x86: fix PEBS issues on Intel Atom/Core2 Stephane Eranian
2016-01-06 18:52 ` [tip:perf/core] " tip-bot for Stephane Eranian
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