From: michael chen <linux-kernel@vger.kernel.org>
To: alan@lxorguk.ukuu.org.uk, torvalds@transmeta.com
Cc: linux-kernel@vger.kernel.org
Subject: About Celeron processor memory barrier problem
Date: Thu, 23 Dec 1999 17:24:43 +0800 [thread overview]
Message-ID: <4015029078.19991223172443@turbolinux.com.cn> (raw)
Hi,
I found that when I compiled the 2.4 kernel with the option
of Pentium III or Pentium 4 on a Celeron's PC, it could cause the
system hang at very beginning boot stage, and I found the problem
is cause by the fact that Intel Celeron doesn't have a real memory
barrier,but when you choose the Pentium III option, the kernel
assume the processor has a real memory barrier.
Here is a patch to fix it:
Merry Christmas :)
Michael Chen
diff -Nur linux/include/asm-i386/system.h linux.new/include/asm-i386/system.h
--- linux/include/asm-i386/system.h Mon Dec 11 19:26:39 2000
+++ linux.new/include/asm-i386/system.h Sat Dec 23 16:06:01 2000
@@ -274,7 +274,14 @@
#ifndef CONFIG_X86_XMM
#define mb() __asm__ __volatile__ ("lock; addl $0,0(%%esp)": : :"memory")
#else
-#define mb() __asm__ __volatile__ ("sfence": : :"memory")
+#define mb() do { \
+ if ( cpu_has_xmm ) { \
+ asm volatile("sfence": : :"memory"); \
+ } \
+ else { \
+ asm volatile("lock; addl $0,0(%%esp)": : :"memory"); \
+ } \
+} while (0)
#endif
#define rmb() mb()
#define wmb() __asm__ __volatile__ ("": : :"memory")
diff -Nur linux/include/linux/tqueue.h linux.new/include/linux/tqueue.h
--- linux/include/linux/tqueue.h Sat Dec 23 16:16:44 2000
+++ linux.new/include/linux/tqueue.h Sat Dec 23 16:06:01 2000
@@ -17,6 +17,7 @@
#include <linux/list.h>
#include <asm/bitops.h>
#include <asm/system.h>
+#include <asm/processor.h>
/*
* New proposed "bottom half" handlers:
diff -Nur linux/include/asm-i386/system.h linux.new/include/asm-i386/system.h
--- linux/include/asm-i386/system.h Mon Dec 11 19:26:39 2000
+++ linux.new/include/asm-i386/system.h Sat Dec 23 16:06:01 2000
@@ -274,7 +274,14 @@
#ifndef CONFIG_X86_XMM
#define mb() __asm__ __volatile__ ("lock; addl $0,0(%%esp)": : :"memory")
#else
-#define mb() __asm__ __volatile__ ("sfence": : :"memory")
+#define mb() do { \
+ if ( cpu_has_xmm ) { \
+ asm volatile("sfence": : :"memory"); \
+ } \
+ else { \
+ asm volatile("lock; addl $0,0(%%esp)": : :"memory"); \
+ } \
+} while (0)
#endif
#define rmb() mb()
#define wmb() __asm__ __volatile__ ("": : :"memory")
diff -Nur linux/include/linux/tqueue.h linux.new/include/linux/tqueue.h
--- linux/include/linux/tqueue.h Sat Dec 23 16:16:44 2000
+++ linux.new/include/linux/tqueue.h Sat Dec 23 16:06:01 2000
@@ -17,6 +17,7 @@
#include <linux/list.h>
#include <asm/bitops.h>
#include <asm/system.h>
+#include <asm/processor.h>
/*
* New proposed "bottom half" handlers:
-
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next reply other threads:[~2000-12-23 9:55 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
1999-12-23 9:24 michael chen [this message]
2000-12-23 11:04 ` About Celeron processor memory barrier problem Erik Mouw
2000-12-23 17:21 ` Linus Torvalds
2000-12-23 23:27 ` Erik Mouw
2000-12-24 9:45 ` Jeffrey Rose
2000-12-24 11:48 ` Erik Mouw
2000-12-23 23:36 ` Matthias Schniedermeyer
2000-12-24 9:36 ` Kai Henningsen
2000-12-24 20:50 ` Tim Wright
2000-12-24 22:25 ` Linus Torvalds
2000-12-25 2:38 ` Tim Wright
2000-12-25 7:19 ` The Doctor What
2000-12-26 1:40 ` Alan Cox
2000-12-26 18:14 ` Linus Torvalds
2000-12-26 22:31 ` Rogier Wolff
2001-01-01 11:55 ` Riley Williams
2000-12-26 0:15 ` Albert D. Cahalan
2000-12-25 11:12 ` Kai Henningsen
2000-12-25 19:37 ` Ian Stirling
2000-12-26 20:38 ` Pavel Machek
2000-12-23 22:34 ` Pavel Machek
[not found] <fa.gm0b5nv.1h2mope@ifi.uio.no>
[not found] ` <fa.n7l96dv.2nah0l@ifi.uio.no>
2000-12-26 19:24 ` Giacomo Catenazzi
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