KVM: x86: Expose more Intel AVX512 feature to guest
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Message ID 1470124878-19361-1-git-send-email-luwei.kang@intel.com
State New, archived
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Series
  • KVM: x86: Expose more Intel AVX512 feature to guest
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Commit Message

Kang, Luwei Aug. 2, 2016, 8:01 a.m. UTC
Expose AVX512DQ, AVX512BW, AVX512VL feature to guest.
Its spec can be found at:
https://software.intel.com/sites/default/files/managed/b4/3a/319433-024.pdf

Signed-off-by: Luwei Kang <luwei.kang@intel.com>
---
 arch/x86/kvm/cpuid.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

Comments

Kang, Luwei Aug. 11, 2016, 7:32 a.m. UTC | #1
> Expose AVX512DQ, AVX512BW, AVX512VL feature to guest.
> Its spec can be found at:
> https://software.intel.com/sites/default/files/managed/b4/3a/319433-024.pdf
> 
> Signed-off-by: Luwei Kang <luwei.kang@intel.com>
> ---
>  arch/x86/kvm/cpuid.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 7597b42..a2d007c 100644
> --- a/arch/x86/kvm/cpuid.c
> +++ b/arch/x86/kvm/cpuid.c
> @@ -366,7 +366,8 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
>  		F(FSGSBASE) | F(BMI1) | F(HLE) | F(AVX2) | F(SMEP) |
>  		F(BMI2) | F(ERMS) | f_invpcid | F(RTM) | f_mpx | F(RDSEED) |
>  		F(ADX) | F(SMAP) | F(AVX512F) | F(AVX512PF) | F(AVX512ER) |
> -		F(AVX512CD) | F(CLFLUSHOPT) | F(CLWB) | F(PCOMMIT);
> +		F(AVX512CD) | F(CLFLUSHOPT) | F(CLWB) | F(PCOMMIT) |
> +		F(AVX512DQ) | F(AVX512BW) | F(AVX512VL);
> 

Hi Paolo,
    What is your opinion?

>  	/* cpuid 0xD.1.eax */
>  	const u32 kvm_cpuid_D_1_eax_x86_features =
> --
> 2.7.4
Paolo Bonzini Aug. 11, 2016, 1:24 p.m. UTC | #2
> > Expose AVX512DQ, AVX512BW, AVX512VL feature to guest.
> > Its spec can be found at:
> > https://software.intel.com/sites/default/files/managed/b4/3a/319433-024.pdf
> > 
> > Signed-off-by: Luwei Kang <luwei.kang@intel.com>
> > ---
> >  arch/x86/kvm/cpuid.c | 3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> > 
> > diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index
> > 7597b42..a2d007c 100644
> > --- a/arch/x86/kvm/cpuid.c
> > +++ b/arch/x86/kvm/cpuid.c
> > @@ -366,7 +366,8 @@ static inline int __do_cpuid_ent(struct
> > kvm_cpuid_entry2 *entry, u32 function,
> >  		F(FSGSBASE) | F(BMI1) | F(HLE) | F(AVX2) | F(SMEP) |
> >  		F(BMI2) | F(ERMS) | f_invpcid | F(RTM) | f_mpx | F(RDSEED) |
> >  		F(ADX) | F(SMAP) | F(AVX512F) | F(AVX512PF) | F(AVX512ER) |
> > -		F(AVX512CD) | F(CLFLUSHOPT) | F(CLWB) | F(PCOMMIT);
> > +		F(AVX512CD) | F(CLFLUSHOPT) | F(CLWB) | F(PCOMMIT) |
> > +		F(AVX512DQ) | F(AVX512BW) | F(AVX512VL);
> > 
> 
> Hi Paolo,
>     What is your opinion?

Hi, the patch was sent too late for 4.8 so I just ignored it. :)  Radim
is handling the tree now and I guess he'll get to it in the next few
days.  It's a trivial patch, so I don't expect any issue.

Paolo
Radim Krčmář Aug. 11, 2016, 2:40 p.m. UTC | #3
2016-08-11 09:24-0400, Paolo Bonzini:
>> > Expose AVX512DQ, AVX512BW, AVX512VL feature to guest.
>> > Its spec can be found at:
>> > https://software.intel.com/sites/default/files/managed/b4/3a/319433-024.pdf
>> > 
>> > Signed-off-by: Luwei Kang <luwei.kang@intel.com>
>> > ---
>> >  arch/x86/kvm/cpuid.c | 3 ++-
>> >  1 file changed, 2 insertions(+), 1 deletion(-)
>> > 
>> > diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index
>> > 7597b42..a2d007c 100644
>> > --- a/arch/x86/kvm/cpuid.c
>> > +++ b/arch/x86/kvm/cpuid.c
>> > @@ -366,7 +366,8 @@ static inline int __do_cpuid_ent(struct
>> > kvm_cpuid_entry2 *entry, u32 function,
>> >  		F(FSGSBASE) | F(BMI1) | F(HLE) | F(AVX2) | F(SMEP) |
>> >  		F(BMI2) | F(ERMS) | f_invpcid | F(RTM) | f_mpx | F(RDSEED) |
>> >  		F(ADX) | F(SMAP) | F(AVX512F) | F(AVX512PF) | F(AVX512ER) |
>> > -		F(AVX512CD) | F(CLFLUSHOPT) | F(CLWB) | F(PCOMMIT);
>> > +		F(AVX512CD) | F(CLFLUSHOPT) | F(CLWB) | F(PCOMMIT) |
>> > +		F(AVX512DQ) | F(AVX512BW) | F(AVX512VL);
>> > 
>> 
>> Hi Paolo,
>>     What is your opinion?
> 
> Hi, the patch was sent too late for 4.8 so I just ignored it. :)  Radim
> is handling the tree now and I guess he'll get to it in the next few
> days.  It's a trivial patch, so I don't expect any issue.

F(PCOMMIT) was removed in dfa169bbee00 ("Revert "KVM: x86: add pcommit
support""), so the patch doesn't apply.

I made minor changes (see below) and queued for 4.9, thanks.

-		F(AVX512CD) | F(CLFLUSHOPT) | F(CLWB);
+		F(AVX512CD) | F(CLFLUSHOPT) | F(CLWB) | F(AVX512DQ) |
+		F(AVX512BW) | F(AVX512VL);

Patch
diff mbox series

diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 7597b42..a2d007c 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -366,7 +366,8 @@  static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
 		F(FSGSBASE) | F(BMI1) | F(HLE) | F(AVX2) | F(SMEP) |
 		F(BMI2) | F(ERMS) | f_invpcid | F(RTM) | f_mpx | F(RDSEED) |
 		F(ADX) | F(SMAP) | F(AVX512F) | F(AVX512PF) | F(AVX512ER) |
-		F(AVX512CD) | F(CLFLUSHOPT) | F(CLWB) | F(PCOMMIT);
+		F(AVX512CD) | F(CLFLUSHOPT) | F(CLWB) | F(PCOMMIT) |
+		F(AVX512DQ) | F(AVX512BW) | F(AVX512VL);
 
 	/* cpuid 0xD.1.eax */
 	const u32 kvm_cpuid_D_1_eax_x86_features =