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From: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Cc: Will.Deacon@arm.com, catalin.marinas@arm.com,
	mark.rutland@arm.com, acme@kernel.org,
	alexander.shishkin@linux.intel.com, peterz@infradead.org,
	mingo@redhat.com, jnair@caviumnetworks.com, gpkulkarni@gmail.com
Subject: [PATCH 3/3] perf tool, arm64, thunderx2: Add implementation defined events for ThunderX2
Date: Tue,  4 Apr 2017 13:06:43 +0530	[thread overview]
Message-ID: <1491291403-29893-4-git-send-email-ganapatrao.kulkarni@cavium.com> (raw)
In-Reply-To: <1491291403-29893-1-git-send-email-ganapatrao.kulkarni@cavium.com>

This is not a full event list, but a short list of useful events.

Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
---
 tools/perf/pmu-events/arch/arm64/mapfile.csv       |  2 +
 .../arm64/thunderx2/implementation-defined.json    | 72 ++++++++++++++++++++++
 2 files changed, 74 insertions(+)
 create mode 100644 tools/perf/pmu-events/arch/arm64/mapfile.csv
 create mode 100644 tools/perf/pmu-events/arch/arm64/thunderx2/implementation-defined.json

diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
new file mode 100644
index 0000000..ba30e43
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
@@ -0,0 +1,2 @@
+Family-model,Version,Filename,EventType
+0x00000000420f5161,v1,thunderx2,core
diff --git a/tools/perf/pmu-events/arch/arm64/thunderx2/implementation-defined.json b/tools/perf/pmu-events/arch/arm64/thunderx2/implementation-defined.json
new file mode 100644
index 0000000..360e084
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/thunderx2/implementation-defined.json
@@ -0,0 +1,72 @@
+[
+    {
+        "PublicDescription": "Attributable Level 1 data cache access, read",
+        "EventCode": "0x40",
+        "EventName": "l1d_cache_access_read",
+        "BriefDescription": "l1d cache access, read",
+	"CPU" :"armv8_pmuv3_0"
+    },
+    {
+        "PublicDescription": "Attributable Level 1 data cache access, write ",
+        "EventCode": "0x41",
+        "EventName": "l1d_cache_access_write",
+        "BriefDescription": "l1d cache access, write",
+	"CPU" :"armv8_pmuv3_0"
+    },
+    {
+        "PublicDescription": "Attributable Level 1 data cache refill, read",
+        "EventCode": "0x42",
+        "EventName": "l1d_cache_refill_read",
+        "BriefDescription": "l1d cache refill, read",
+	"CPU" :"armv8_pmuv3_0"
+    },
+    {
+        "PublicDescription": "Attributable Level 1 data cache refill, write",
+        "EventCode": "0x43",
+        "EventName": "l1d_cache_refill_write",
+        "BriefDescription": "l1d refill, write",
+	"CPU" :"armv8_pmuv3_0"
+    },
+    {
+        "PublicDescription": "Attributable Level 1 data TLB refill, read",
+        "EventCode": "0x4C",
+        "EventName": "l1d_tlb_refill_read",
+        "BriefDescription": "l1d tlb refill, read",
+	"CPU" :"armv8_pmuv3_0"
+    },
+    {
+        "PublicDescription": "Attributable Level 1 data TLB refill, write",
+        "EventCode": "0x4D",
+        "EventName": "l1d_tlb_refill_write",
+        "BriefDescription": "l1d tlb refill, write",
+	"CPU" :"armv8_pmuv3_0"
+    },
+    {
+        "PublicDescription": "Attributable Level 1 data or unified TLB access, read",
+        "EventCode": "0x4E",
+        "EventName": "l1d_tlb_read",
+        "BriefDescription": "l1d tlb, read",
+	"CPU" :"armv8_pmuv3_0"
+    },
+    {
+        "PublicDescription": "Attributable Level 1 data or unified TLB access, write",
+        "EventCode": "0x4F",
+        "EventName": "l1d_tlb_write",
+        "BriefDescription": "l1d tlb, write",
+	"CPU" :"armv8_pmuv3_0"
+    },
+    {
+        "PublicDescription": "Bus access, read",
+        "EventCode": "0x60",
+        "EventName": "bus_access_read",
+        "BriefDescription": "Bus access, read",
+	"CPU" :"armv8_pmuv3_0"
+   },
+   {
+        "PublicDescription": "Bus access, write",
+        "EventCode": "0x61",
+        "EventName": "bus_access_write",
+        "BriefDescription": "Bus access, write",
+	"CPU" :"armv8_pmuv3_0"
+   }
+]
-- 
1.8.1.4

  parent reply	other threads:[~2017-04-04  7:37 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-04-04  7:36 [PATCH 0/3] Add support for ThunderX2 pmu events using json files Ganapatrao Kulkarni
2017-04-04  7:36 ` [PATCH 1/3] perf jevents: Add support to use core pmu name other than cpu Ganapatrao Kulkarni
2017-04-04  7:36 ` [PATCH 2/3] perf tools arm64: implement function get_cpuid_str Ganapatrao Kulkarni
2017-04-04 12:25   ` Mark Rutland
2017-04-05  9:18     ` Ganapatrao Kulkarni
2017-04-04  7:36 ` Ganapatrao Kulkarni [this message]
2017-04-04 12:28   ` [PATCH 3/3] perf tool, arm64, thunderx2: Add implementation defined events for ThunderX2 Mark Rutland
2017-04-05  9:12     ` Ganapatrao Kulkarni
2017-04-05 10:05       ` Mark Rutland
2017-04-06  4:20         ` Ganapatrao Kulkarni
2017-04-06  9:55           ` Mark Rutland
2017-04-19 18:07             ` Ganapatrao Kulkarni
2017-04-20  8:53               ` Mark Rutland
2017-04-04 12:29 ` [PATCH 0/3] Add support for ThunderX2 pmu events using json files Mark Rutland

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