From: anil.s.keshavamurthy@intel.com
To: linux-kernel@vger.kernel.org
Cc: akpm@osdl.org, ak@suse.de, gregkh@suse.de, muli@il.ibm.com,
asit.k.mallick@intel.com, suresh.b.siddha@intel.com,
anil.s.keshavamurthy@intel.com, arjan@linux.intel.com,
ashok.raj@intel.com, shaohua.li@intel.com, davem@davemloft.net
Subject: [Intel-IOMMU 04/10] clflush_cache_range now takes size param
Date: Mon, 04 Jun 2007 14:02:46 -0700 [thread overview]
Message-ID: <20070604210644.316205000@askeshav-devel.jf.intel.com> (raw)
In-Reply-To: 20070604210242.079459000@askeshav-devel.jf.intel.com
[-- Attachment #1: clflush_cache_range.patch --]
[-- Type: text/plain, Size: 1703 bytes --]
Introduce the size param for clflush_cache_range().
Signed-off-by: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
---
arch/x86_64/mm/pageattr.c | 6 +++---
include/asm-x86_64/cacheflush.h | 1 +
2 files changed, 4 insertions(+), 3 deletions(-)
Index: linux-2.6.22-rc3/arch/x86_64/mm/pageattr.c
===================================================================
--- linux-2.6.22-rc3.orig/arch/x86_64/mm/pageattr.c 2007-06-04 12:27:33.000000000 -0700
+++ linux-2.6.22-rc3/arch/x86_64/mm/pageattr.c 2007-06-04 12:37:30.000000000 -0700
@@ -61,10 +61,10 @@
return base;
}
-static void cache_flush_page(void *adr)
+void clflush_cache_range(void *adr, int size)
{
int i;
- for (i = 0; i < PAGE_SIZE; i += boot_cpu_data.x86_clflush_size)
+ for (i = 0; i < size; i += boot_cpu_data.x86_clflush_size)
asm volatile("clflush (%0)" :: "r" (adr + i));
}
@@ -80,7 +80,7 @@
list_for_each_entry(pg, l, lru) {
void *adr = page_address(pg);
if (cpu_has_clflush)
- cache_flush_page(adr);
+ clflush_cache_range(adr, PAGE_SIZE);
}
__flush_tlb_all();
}
Index: linux-2.6.22-rc3/include/asm-x86_64/cacheflush.h
===================================================================
--- linux-2.6.22-rc3.orig/include/asm-x86_64/cacheflush.h 2007-06-04 12:27:33.000000000 -0700
+++ linux-2.6.22-rc3/include/asm-x86_64/cacheflush.h 2007-06-04 12:37:30.000000000 -0700
@@ -27,6 +27,7 @@
void global_flush_tlb(void);
int change_page_attr(struct page *page, int numpages, pgprot_t prot);
int change_page_attr_addr(unsigned long addr, int numpages, pgprot_t prot);
+void clflush_cache_range(void *addr, int size);
#ifdef CONFIG_DEBUG_RODATA
void mark_rodata_ro(void);
--
next prev parent reply other threads:[~2007-06-04 22:31 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-06-04 21:02 [Intel-IOMMU 00/10] Intel IOMMU support anil.s.keshavamurthy
2007-06-04 21:02 ` [Intel-IOMMU 01/10] DMAR detection and parsing logic anil.s.keshavamurthy
2007-06-04 22:54 ` Jeff Garzik
2007-06-04 22:58 ` Keshavamurthy, Anil S
2007-06-04 23:03 ` Jeff Garzik
2007-06-04 23:17 ` Keshavamurthy, Anil S
2007-06-04 21:02 ` [Intel-IOMMU 02/10] Library routines for handling pre-allocated pool of objects anil.s.keshavamurthy
2007-06-04 22:57 ` Jeff Garzik
2007-06-04 23:06 ` Keshavamurthy, Anil S
2007-06-04 23:43 ` Jeff Garzik
2007-06-04 23:51 ` Keshavamurthy, Anil S
2007-06-05 20:24 ` Keshavamurthy, Anil S
2007-06-05 20:30 ` Jeff Garzik
2007-06-05 20:48 ` Keshavamurthy, Anil S
2007-06-04 21:02 ` [Intel-IOMMU 03/10] PCI generic helper function anil.s.keshavamurthy
2007-06-04 21:02 ` anil.s.keshavamurthy [this message]
2007-06-04 21:02 ` [Intel-IOMMU 05/10] IOVA allocation and management routines anil.s.keshavamurthy
2007-06-04 21:02 ` [Intel-IOMMU 06/10] Intel IOMMU driver anil.s.keshavamurthy
2007-06-04 21:02 ` [Intel-IOMMU 07/10] Intel iommu cmdline option - forcedac anil.s.keshavamurthy
2007-06-04 21:02 ` [Intel-IOMMU 08/10] DMAR fault handling support anil.s.keshavamurthy
2007-06-04 21:02 ` [Intel-IOMMU 09/10] Iommu Gfx workaround anil.s.keshavamurthy
2007-06-04 21:02 ` [Intel-IOMMU 10/10] Iommu floppy workaround anil.s.keshavamurthy
2007-06-06 18:56 [Intel-IOMMU 00/10] Intel IOMMU Support anil.s.keshavamurthy
2007-06-06 18:57 ` [Intel-IOMMU 04/10] clflush_cache_range now takes size param anil.s.keshavamurthy
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