From: Palmer Dabbelt <palmer@dabbelt.com>
To: Arnd Bergmann <arnd@arndb.de>,
sfr@canb.auug.org.au, Olof Johansson <olof@lixom.net>
Cc: linux-kernel@vger.kernel.org, patches@groups.riscv.org,
robh+dt@kernel.org, mark.rutland@arm.com, albert@sifive.com,
yamada.masahiro@socionext.com, mmarek@suse.com,
will.deacon@arm.com, peterz@infradead.org, boqun.feng@gmail.com,
oleg@redhat.com, mingo@redhat.com, devicetree@vger.kernel.org,
Palmer Dabbelt <palmer@dabbelt.com>
Subject: [PATCH v9 03/12] dt-bindings: RISC-V CPU Bindings
Date: Tue, 26 Sep 2017 18:56:29 -0700 [thread overview]
Message-ID: <20170927015638.19443-4-palmer@dabbelt.com> (raw)
In-Reply-To: <20170927015638.19443-1-palmer@dabbelt.com>
This patch adds device tree bindings for RISC-V CPUs, patterned after
the ARM device tree CPU bindings.
Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
---
Documentation/devicetree/bindings/riscv/cpus.txt | 162 +++++++++++++++++++++++
1 file changed, 162 insertions(+)
create mode 100644 Documentation/devicetree/bindings/riscv/cpus.txt
diff --git a/Documentation/devicetree/bindings/riscv/cpus.txt b/Documentation/devicetree/bindings/riscv/cpus.txt
new file mode 100644
index 000000000000..adf7b7af5dc3
--- /dev/null
+++ b/Documentation/devicetree/bindings/riscv/cpus.txt
@@ -0,0 +1,162 @@
+===================
+RISC-V CPU Bindings
+===================
+
+The device tree allows to describe the layout of CPUs in a system through
+the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
+defining properties for every cpu.
+
+Bindings for CPU nodes follow the Devicetree Specification, available from:
+
+https://www.devicetree.org/specifications/
+
+with updates for 32-bit and 64-bit RISC-V systems provided in this document.
+
+===========
+Terminology
+===========
+
+This document uses some terminology common to the RISC-V community that is not
+widely used, the definitions of which are listed here:
+
+* hart: A hardware execution context, which contains all the state mandated by
+ the RISC-V ISA: a PC and some registers. This terminology is designed to
+ disambiguate software's view of execution contexts from any particular
+ microarchitectural implementation strategy. For example, my Intel laptop is
+ described as having one socket with two cores, each of which has two hyper
+ threads. Therefore this system has four harts.
+
+=====================================
+cpus and cpu node bindings definition
+=====================================
+
+The RISC-V architecture, in accordance with the Devicetree Specification,
+requires the cpus and cpu nodes to be present and contain the properties
+described below.
+
+- cpus node
+
+ Description: Container of cpu nodes
+
+ The node name must be "cpus".
+
+ A cpus node must define the following properties:
+
+ - #address-cells
+ Usage: required
+ Value type: <u32>
+ Definition: must be set to 1
+ - #size-cells
+ Usage: required
+ Value type: <u32>
+ Definition: must be set to 0
+
+- cpu node
+
+ Description: Describes a hart context
+
+ PROPERTIES
+
+ - device_type
+ Usage: required
+ Value type: <string>
+ Definition: must be "cpu"
+ - reg
+ Usage: required
+ Value type: <u32>
+ Definition: The hart ID of this CPU node
+ - compatible:
+ Usage: required
+ Value type: <stringlist>
+ Definition: must contain "riscv", may contain one of
+ "sifive,rocket0"
+ - mmu-type:
+ Usage: optional
+ Value type: <string>
+ Definition: Specifies the CPU's MMU type. Possible values are
+ "riscv,sv32"
+ "riscv,sv39"
+ "riscv,sv48"
+ - riscv,isa:
+ Usage: required
+ Value type: <string>
+ Definition: Contains the RISC-V ISA string of this hart. These
+ ISA strings are defined by the RISC-V ISA manual.
+
+Example: SiFive Freedom U540G Development Kit
+---------------------------------------------
+
+This system contains two harts: a hart marked as disabled that's used for
+low-level system tasks and should be ignored by Linux, and a second hart that
+Linux is allowed to run on.
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <1000000>;
+ cpu@0 {
+ clock-frequency = <1600000000>;
+ compatible = "sifive,rocket0", "riscv";
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <16384>;
+ next-level-cache = <&L15 &L0>;
+ reg = <0>;
+ riscv,isa = "rv64imac";
+ status = "disabled";
+ L10: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu@1 {
+ clock-frequency = <1600000000>;
+ compatible = "sifive,rocket0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&L15 &L0>;
+ reg = <1>;
+ riscv,isa = "rv64imafdc";
+ status = "okay";
+ tlb-split;
+ L13: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ };
+
+Example: Spike ISA Simulator with 1 Hart
+----------------------------------------
+
+This device tree matches the Spike ISA golden model as run with `spike -p1`.
+
+ cpus {
+ cpu@0 {
+ device_type = "cpu";
+ reg = <0x00000000>;
+ status = "okay";
+ compatible = "riscv";
+ riscv,isa = "rv64imafdc";
+ mmu-type = "riscv,sv48";
+ clock-frequency = <0x3b9aca00>;
+ interrupt-controller {
+ #interrupt-cells = <0x00000001>;
+ interrupt-controller;
+ compatible = "riscv,cpu-intc";
+ }
+ }
+ }
--
2.13.5
next prev parent reply other threads:[~2017-09-27 1:57 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-27 1:56 RISC-V Linux Port v9 Palmer Dabbelt
2017-09-27 1:56 ` [PATCH v9 01/12] MAINTAINERS: Add RISC-V Palmer Dabbelt
2017-09-27 1:56 ` [PATCH v9 02/12] lib: Add shared copies of some GCC library routines Palmer Dabbelt
2017-09-27 1:56 ` Palmer Dabbelt [this message]
2017-10-05 10:16 ` [PATCH v9 03/12] dt-bindings: RISC-V CPU Bindings Mark Rutland
2017-11-20 7:35 ` [patches] " Jonathan Neuschäfer
2017-11-20 19:45 ` Palmer Dabbelt
2017-09-27 1:56 ` [PATCH v9 04/12] RISC-V: Init and Halt Code Palmer Dabbelt
2017-10-05 11:01 ` Mark Rutland
2018-07-30 23:42 ` Palmer Dabbelt
2018-07-31 13:03 ` Mark Rutland
2017-09-27 1:56 ` [PATCH v9 05/12] RISC-V: Atomic and Locking Code Palmer Dabbelt
2017-10-24 14:10 ` Will Deacon
2017-11-14 20:30 ` Palmer Dabbelt
2017-11-15 18:06 ` Will Deacon
2017-11-15 19:48 ` [patches] " Palmer Dabbelt
2017-11-15 23:59 ` Daniel Lustig
2017-11-16 1:19 ` Boqun Feng
2017-11-16 1:31 ` Daniel Lustig
2017-11-16 1:52 ` Boqun Feng
2017-11-16 6:40 ` Daniel Lustig
2017-11-16 10:25 ` Will Deacon
2017-11-16 17:12 ` Daniel Lustig
2017-11-16 2:08 ` Palmer Dabbelt
2017-09-27 1:56 ` [PATCH v9 06/12] RISC-V: Generic library routines and assembly Palmer Dabbelt
2017-09-27 1:56 ` [PATCH v9 07/12] RISC-V: ELF and module implementation Palmer Dabbelt
2017-09-27 1:56 ` [PATCH v9 08/12] RISC-V: Task implementation Palmer Dabbelt
2017-09-27 1:56 ` [PATCH v9 09/12] RISC-V: Device, timer, IRQs, and the SBI Palmer Dabbelt
2017-09-27 1:56 ` [PATCH v9 10/12] RISC-V: Paging and MMU Palmer Dabbelt
2017-09-27 1:56 ` [PATCH v9 11/12] RISC-V: User-facing API Palmer Dabbelt
2017-09-27 1:56 ` [PATCH v9 12/12] RISC-V: Build Infrastructure Palmer Dabbelt
2017-09-27 6:08 ` RISC-V Linux Port v9 Arnd Bergmann
2017-10-05 0:21 ` Palmer Dabbelt
2017-10-05 7:34 ` Arnd Bergmann
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