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From: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Cc: Will.Deacon@arm.com, catalin.marinas@arm.com,
	mark.rutland@arm.com, acme@kernel.org,
	alexander.shishkin@linux.intel.com, peterz@infradead.org,
	mingo@redhat.com, jnair@caviumnetworks.com,
	zhangshaokun@hisilicon.com, Jonathan.Cameron@huawei.com,
	Robert.Richter@cavium.com, gklkml16@gmail.com
Subject: [PATCH v8 4/4] perf vendor events arm64: Add ThunderX2 implementation defined pmu core events
Date: Thu, 12 Oct 2017 19:41:16 +0530	[thread overview]
Message-ID: <20171012141116.32475-5-ganapatrao.kulkarni@cavium.com> (raw)
In-Reply-To: <20171012141116.32475-1-ganapatrao.kulkarni@cavium.com>

This is not a full event list, but a short list of useful events.

Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
---
 .../arch/arm64/cavium/thunderx2-imp-def.json       | 62 ++++++++++++++++++++++
 tools/perf/pmu-events/arch/arm64/mapfile.csv       | 15 ++++++
 2 files changed, 77 insertions(+)
 create mode 100644 tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/mapfile.csv

diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json
new file mode 100644
index 0000000..2db45c4
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json
@@ -0,0 +1,62 @@
+[
+    {
+        "PublicDescription": "Attributable Level 1 data cache access, read",
+        "EventCode": "0x40",
+        "EventName": "l1d_cache_rd",
+        "BriefDescription": "L1D cache read",
+    },
+    {
+        "PublicDescription": "Attributable Level 1 data cache access, write ",
+        "EventCode": "0x41",
+        "EventName": "l1d_cache_wr",
+        "BriefDescription": "L1D cache write",
+    },
+    {
+        "PublicDescription": "Attributable Level 1 data cache refill, read",
+        "EventCode": "0x42",
+        "EventName": "l1d_cache_refill_rd",
+        "BriefDescription": "L1D cache refill read",
+    },
+    {
+        "PublicDescription": "Attributable Level 1 data cache refill, write",
+        "EventCode": "0x43",
+        "EventName": "l1d_cache_refill_wr",
+        "BriefDescription": "L1D refill write",
+    },
+    {
+        "PublicDescription": "Attributable Level 1 data TLB refill, read",
+        "EventCode": "0x4C",
+        "EventName": "l1d_tlb_refill_rd",
+        "BriefDescription": "L1D tlb refill read",
+    },
+    {
+        "PublicDescription": "Attributable Level 1 data TLB refill, write",
+        "EventCode": "0x4D",
+        "EventName": "l1d_tlb_refill_wr",
+        "BriefDescription": "L1D tlb refill write",
+    },
+    {
+        "PublicDescription": "Attributable Level 1 data or unified TLB access, read",
+        "EventCode": "0x4E",
+        "EventName": "l1d_tlb_rd",
+        "BriefDescription": "L1D tlb read",
+    },
+    {
+        "PublicDescription": "Attributable Level 1 data or unified TLB access, write",
+        "EventCode": "0x4F",
+        "EventName": "l1d_tlb_wr",
+        "BriefDescription": "L1D tlb write",
+    },
+    {
+        "PublicDescription": "Bus access read",
+        "EventCode": "0x60",
+        "EventName": "bus_access_rd",
+        "BriefDescription": "Bus access read",
+   },
+   {
+        "PublicDescription": "Bus access write",
+        "EventCode": "0x61",
+        "EventName": "bus_access_wr",
+        "BriefDescription": "Bus access write",
+   }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
new file mode 100644
index 0000000..219d675
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
@@ -0,0 +1,15 @@
+# Format:
+#	MIDR,Version,JSON/file/pathname,Type
+#
+# where
+#	MIDR	Processor version
+#		Variant[23:20] and Revision [3:0] should be zero.
+#	Version could be used to track version of of JSON file
+#		but currently unused.
+#	JSON/file/pathname is the path to JSON file, relative
+#		to tools/perf/pmu-events/arch/arm64/.
+#	Type is core, uncore etc
+#
+#
+#Family-model,Version,Filename,EventType
+0x00000000420f5160,v1,cavium,core
-- 
2.9.4

  parent reply	other threads:[~2017-10-12 14:12 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-10-12 14:11 [PATCH v8 0/4] Add support for ThunderX2 pmu events using json files Ganapatrao Kulkarni
2017-10-12 14:11 ` [PATCH v8 1/4] perf utils: passing pmu as a parameter to function get_cpuid_str Ganapatrao Kulkarni
2017-10-12 14:11 ` [PATCH v8 2/4] perf tools arm64: Add support for get_cpuid_str function Ganapatrao Kulkarni
2017-10-12 14:11 ` [PATCH v8 3/4] perf utils: Add helper function is_pmu_core to detect PMU CORE devices Ganapatrao Kulkarni
2017-10-12 14:11 ` Ganapatrao Kulkarni [this message]
2017-10-12 15:24 ` [PATCH v8 0/4] Add support for ThunderX2 pmu events using json files Will Deacon
2017-10-12 17:24   ` Ganapatrao Kulkarni
2017-10-13  9:11     ` Will Deacon
2017-10-13 13:04       ` Arnaldo Carvalho de Melo
2017-10-13 19:33         ` Arnaldo Carvalho de Melo

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