From: Matt Redfearn <matt.redfearn@mips.com>
To: Ralf Baechle <ralf@linux-mips.org>, Thomas Gleixner <tglx@linutronix.de>
Cc: <linux-mips@linux-mips.org>,
Matt Redfearn <matt.redfearn@mips.com>,
"Marc Zyngier" <marc.zyngier@arm.com>,
Jason Cooper <jason@lakedaemon.net>,
<linux-kernel@vger.kernel.org>
Subject: [PATCH 4/6] irqchip/mips-gic: Always attempt to enable EIC mode
Date: Fri, 5 Jan 2018 10:31:08 +0000 [thread overview]
Message-ID: <1515148270-9391-5-git-send-email-matt.redfearn@mips.com> (raw)
In-Reply-To: <1515148270-9391-1-git-send-email-matt.redfearn@mips.com>
The MIPS GIC supports running in External Interrupt Controller (EIC)
mode, in which the GIC can raise up to 64 separate interrupts rather
than the usual 6. This mode is enabled by setting bit GIC_VL_CTL.EIC. If
the bit sticks, then EIC mode is present and becomes enabled. Otherwise
this bit is read-only 0 and setting it will have no effect.
The CP0 register Config3 bit VEIC indicates the status of EIC mode, and
effectively reflects GIC_VL_CTL.EIC. After attempting to enable EIC
mode, read back Config3.VEIC to determine if VEIC mode is present and
has been activated. If so, update the boot CPU flags to reflect that
VEIC mode is now active.
Signed-off-by: Matt Redfearn <matt.redfearn@mips.com>
---
drivers/irqchip/irq-mips-gic.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
index ef92a4d2038e..ee391f42e97d 100644
--- a/drivers/irqchip/irq-mips-gic.c
+++ b/drivers/irqchip/irq-mips-gic.c
@@ -725,6 +725,9 @@ static int __init gic_of_init(struct device_node *node,
gic_shared_intrs >>= __ffs(GIC_CONFIG_NUMINTERRUPTS);
gic_shared_intrs = (gic_shared_intrs + 1) * 8;
+ /* Enable EIC mode if supported. */
+ mips_gic_enable_eic();
+
if (cpu_has_veic) {
/* Always use vector 1 in EIC mode */
gic_cpu_pin = 0;
--
2.7.4
next prev parent reply other threads:[~2018-01-05 10:33 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-05 10:31 [PATCH 0/6] irqchip/mips-gic: Enable & use VEIC mode if available Matt Redfearn
2018-01-05 10:31 ` [PATCH 1/6] MIPS: Move ehb() to barrier.h Matt Redfearn
2018-05-17 14:30 ` James Hogan
2018-01-05 10:31 ` [PATCH 2/6] MIPS: CPS: Introduce mips_gic_enable_eic Matt Redfearn
2018-01-05 10:31 ` [PATCH 3/6] MIPS: Generic: Support GIC in EIC mode Matt Redfearn
2018-02-05 14:11 ` James Hogan
2018-01-05 10:31 ` Matt Redfearn [this message]
2018-01-05 10:31 ` [PATCH 5/6] irqchip/mips-gic: Use separate vector for shared interrupts " Matt Redfearn
2018-01-05 10:31 ` [PATCH 6/6] irqchip/mips-gic: Separate local interrupt handling Matt Redfearn
2018-03-14 11:15 ` [PATCH 0/6] irqchip/mips-gic: Enable & use VEIC mode if available Marc Zyngier
2018-03-14 15:46 ` James Hogan
2018-03-14 15:53 ` Marc Zyngier
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1515148270-9391-5-git-send-email-matt.redfearn@mips.com \
--to=matt.redfearn@mips.com \
--cc=jason@lakedaemon.net \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mips@linux-mips.org \
--cc=marc.zyngier@arm.com \
--cc=ralf@linux-mips.org \
--cc=tglx@linutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).