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From: Paul Cercueil <paul@crapouillou.net>
To: Ralf Baechle <ralf@linux-mips.org>
Cc: Maarten ter Huurne <maarten@treewalker.org>,
	Paul Burton <paul.burton@mips.com>,
	linux-kernel@vger.kernel.org, linux-mips@linux-mips.org,
	Paul Cercueil <paul@crapouillou.net>
Subject: [PATCH v6 04/15] clk: ingenic: Add code to enable/disable PLLs
Date: Fri,  5 Jan 2018 19:25:02 +0100	[thread overview]
Message-ID: <20180105182513.16248-5-paul@crapouillou.net> (raw)
In-Reply-To: <20180105182513.16248-1-paul@crapouillou.net>

This commit permits the PLLs to be dynamically enabled and disabled when
their children clocks are enabled and disabled.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
---
 drivers/clk/ingenic/cgu.c | 89 +++++++++++++++++++++++++++++++++++++++--------
 1 file changed, 74 insertions(+), 15 deletions(-)

 v2: No change
 v3: No change
 v4: No change
 v5: No change
 v6: No change

diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c
index 381c4a17a1fc..56a712c9075f 100644
--- a/drivers/clk/ingenic/cgu.c
+++ b/drivers/clk/ingenic/cgu.c
@@ -107,9 +107,6 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 	if (bypass)
 		return parent_rate;
 
-	if (!enable)
-		return 0;
-
 	for (od = 0; od < pll_info->od_max; od++) {
 		if (pll_info->od_encoding[od] == od_enc)
 			break;
@@ -153,17 +150,25 @@ ingenic_pll_calc(const struct ingenic_cgu_clk_info *clk_info,
 	return div_u64((u64)parent_rate * m, n * od);
 }
 
-static long
-ingenic_pll_round_rate(struct clk_hw *hw, unsigned long req_rate,
-		       unsigned long *prate)
+static inline const struct ingenic_cgu_clk_info *to_clk_info(
+		struct ingenic_clk *ingenic_clk)
 {
-	struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
 	struct ingenic_cgu *cgu = ingenic_clk->cgu;
 	const struct ingenic_cgu_clk_info *clk_info;
 
 	clk_info = &cgu->clock_info[ingenic_clk->idx];
 	BUG_ON(clk_info->type != CGU_CLK_PLL);
 
+	return clk_info;
+}
+
+static long
+ingenic_pll_round_rate(struct clk_hw *hw, unsigned long req_rate,
+		       unsigned long *prate)
+{
+	struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
+	const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
+
 	return ingenic_pll_calc(clk_info, req_rate, *prate, NULL, NULL, NULL);
 }
 
@@ -171,19 +176,14 @@ static int
 ingenic_pll_set_rate(struct clk_hw *hw, unsigned long req_rate,
 		     unsigned long parent_rate)
 {
-	const unsigned timeout = 100;
 	struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
 	struct ingenic_cgu *cgu = ingenic_clk->cgu;
-	const struct ingenic_cgu_clk_info *clk_info;
-	const struct ingenic_cgu_pll_info *pll_info;
+	const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
+	const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll;
 	unsigned long rate, flags;
-	unsigned m, n, od, i;
+	unsigned int m, n, od;
 	u32 ctl;
 
-	clk_info = &cgu->clock_info[ingenic_clk->idx];
-	BUG_ON(clk_info->type != CGU_CLK_PLL);
-	pll_info = &clk_info->pll;
-
 	rate = ingenic_pll_calc(clk_info, req_rate, parent_rate,
 			       &m, &n, &od);
 	if (rate != req_rate)
@@ -202,6 +202,26 @@ ingenic_pll_set_rate(struct clk_hw *hw, unsigned long req_rate,
 	ctl &= ~(GENMASK(pll_info->od_bits - 1, 0) << pll_info->od_shift);
 	ctl |= pll_info->od_encoding[od - 1] << pll_info->od_shift;
 
+	writel(ctl, cgu->base + pll_info->reg);
+	spin_unlock_irqrestore(&cgu->lock, flags);
+
+	return 0;
+}
+
+static int ingenic_pll_enable(struct clk_hw *hw)
+{
+	struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
+	struct ingenic_cgu *cgu = ingenic_clk->cgu;
+	const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
+	const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll;
+	const unsigned int timeout = 100;
+	unsigned long flags;
+	unsigned int i;
+	u32 ctl;
+
+	spin_lock_irqsave(&cgu->lock, flags);
+	ctl = readl(cgu->base + pll_info->reg);
+
 	ctl &= ~BIT(pll_info->bypass_bit);
 	ctl |= BIT(pll_info->enable_bit);
 
@@ -223,10 +243,48 @@ ingenic_pll_set_rate(struct clk_hw *hw, unsigned long req_rate,
 	return 0;
 }
 
+static void ingenic_pll_disable(struct clk_hw *hw)
+{
+	struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
+	struct ingenic_cgu *cgu = ingenic_clk->cgu;
+	const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
+	const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll;
+	unsigned long flags;
+	u32 ctl;
+
+	spin_lock_irqsave(&cgu->lock, flags);
+	ctl = readl(cgu->base + pll_info->reg);
+
+	ctl &= ~BIT(pll_info->enable_bit);
+
+	writel(ctl, cgu->base + pll_info->reg);
+	spin_unlock_irqrestore(&cgu->lock, flags);
+}
+
+static int ingenic_pll_is_enabled(struct clk_hw *hw)
+{
+	struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
+	struct ingenic_cgu *cgu = ingenic_clk->cgu;
+	const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
+	const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll;
+	unsigned long flags;
+	u32 ctl;
+
+	spin_lock_irqsave(&cgu->lock, flags);
+	ctl = readl(cgu->base + pll_info->reg);
+	spin_unlock_irqrestore(&cgu->lock, flags);
+
+	return !!(ctl & BIT(pll_info->enable_bit));
+}
+
 static const struct clk_ops ingenic_pll_ops = {
 	.recalc_rate = ingenic_pll_recalc_rate,
 	.round_rate = ingenic_pll_round_rate,
 	.set_rate = ingenic_pll_set_rate,
+
+	.enable = ingenic_pll_enable,
+	.disable = ingenic_pll_disable,
+	.is_enabled = ingenic_pll_is_enabled,
 };
 
 /*
@@ -601,6 +659,7 @@ static int ingenic_register_clock(struct ingenic_cgu *cgu, unsigned idx)
 		}
 	} else if (caps & CGU_CLK_PLL) {
 		clk_init.ops = &ingenic_pll_ops;
+		clk_init.flags |= CLK_SET_RATE_GATE;
 
 		caps &= ~CGU_CLK_PLL;
 
-- 
2.11.0

  parent reply	other threads:[~2018-01-05 18:25 UTC|newest]

Thread overview: 73+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-01-02 15:08 [PATCH v5 01/15] clk: ingenic: Use const pointer to clk_ops in struct Paul Cercueil
2018-01-02 15:08 ` [PATCH v5 02/15] clk: ingenic: Fix recalc_rate for clocks with fixed divider Paul Cercueil
2018-01-02 15:08 ` [PATCH v5 03/15] clk: ingenic: support PLLs with no bypass bit Paul Cercueil
2018-01-02 15:08 ` [PATCH v5 04/15] clk: ingenic: Add code to enable/disable PLLs Paul Cercueil
2018-01-02 15:08 ` [PATCH v5 05/15] dt-bindings: clock: Add jz4770-cgu.h header Paul Cercueil
2018-01-05 16:34   ` Rob Herring
2018-01-02 15:08 ` [PATCH v5 06/15] clk: Add Ingenic jz4770 CGU driver Paul Cercueil
2018-01-02 15:08 ` [PATCH v5 07/15] MIPS: Setup boot_command_line before plat_mem_setup Paul Cercueil
2018-01-02 17:05   ` Mathieu Malaterre
2018-01-02 15:08 ` [PATCH v5 08/15] MIPS: ingenic: Use common cmdline handling code Paul Cercueil
2018-01-02 15:58   ` PrasannaKumar Muralidharan
2018-01-02 15:08 ` [PATCH v5 09/15] MIPS: platform: add machtype IDs for more Ingenic SoCs Paul Cercueil
2018-01-02 15:59   ` PrasannaKumar Muralidharan
2018-01-02 15:08 ` [PATCH v5 10/15] MIPS: ingenic: Add machine info for supported boards Paul Cercueil
2018-01-02 16:02   ` PrasannaKumar Muralidharan
2018-01-02 16:32     ` Paul Cercueil
2018-01-02 15:08 ` [PATCH v5 11/15] MIPS: ingenic: Initial JZ4770 support Paul Cercueil
2018-01-02 16:09   ` PrasannaKumar Muralidharan
2018-01-02 15:08 ` [PATCH v5 12/15] MIPS: JZ4770: Work around config2 misreporting associativity Paul Cercueil
2018-01-02 15:08 ` [PATCH v5 13/15] MIPS: JZ4770: Workaround for corrupted DMA transfers Paul Cercueil
2018-01-02 16:45   ` PrasannaKumar Muralidharan
2018-01-05 18:03     ` Paul Cercueil
2018-01-02 15:08 ` [PATCH v5 14/15] devicetree/bindings: Add GCW vendor prefix Paul Cercueil
2018-01-02 15:08 ` [PATCH v5 15/15] MIPS: ingenic: Initial GCW Zero support Paul Cercueil
2018-01-02 17:04   ` Mathieu Malaterre
2018-01-05 18:24 ` [PATCH v6 00/15] JZ4770 SoC support Paul Cercueil
2018-01-05 18:24   ` [PATCH v6 01/15] clk: ingenic: Use const pointer to clk_ops in struct Paul Cercueil
2018-01-16 15:47     ` [PATCH v7 00/14] JZ4770 and GCW0 patchset Paul Cercueil
2018-01-16 15:47       ` [PATCH v7 01/14] clk: ingenic: Use const pointer to clk_ops in struct Paul Cercueil
2018-01-16 15:47       ` [PATCH v7 02/14] clk: ingenic: Fix recalc_rate for clocks with fixed divider Paul Cercueil
2018-01-16 15:47       ` [PATCH v7 03/14] clk: ingenic: support PLLs with no bypass bit Paul Cercueil
2018-01-16 15:47       ` [PATCH v7 04/14] clk: ingenic: Add code to enable/disable PLLs Paul Cercueil
2018-01-16 15:47       ` [PATCH v7 05/14] dt-bindings: clock: Add jz4770-cgu.h header Paul Cercueil
2018-01-16 15:47       ` [PATCH v7 06/14] clk: Add Ingenic jz4770 CGU driver Paul Cercueil
2018-01-16 15:47       ` [PATCH v7 07/14] MIPS: Setup boot_command_line before plat_mem_setup Paul Cercueil
2018-01-16 15:47       ` [PATCH v7 08/14] MIPS: ingenic: Use common cmdline handling code Paul Cercueil
2018-01-16 15:47       ` [PATCH v7 09/14] MIPS: platform: add machtype IDs for more Ingenic SoCs Paul Cercueil
2018-01-16 15:48       ` [PATCH v7 10/14] MIPS: ingenic: Detect machtype from SoC compatible string Paul Cercueil
2018-01-16 22:06         ` James Hogan
2018-01-16 15:48       ` [PATCH v7 11/14] MIPS: ingenic: Initial JZ4770 support Paul Cercueil
2018-01-17 21:28         ` James Hogan
2018-01-18 17:14           ` Paul Cercueil
2018-01-18 20:30             ` James Hogan
2018-01-16 15:48       ` [PATCH v7 12/14] MIPS: JZ4770: Work around config2 misreporting associativity Paul Cercueil
2018-01-16 15:48       ` [PATCH v7 13/14] devicetree/bindings: Add GCW vendor prefix Paul Cercueil
2018-01-16 15:48       ` [PATCH v7 14/14] MIPS: ingenic: Initial GCW Zero support Paul Cercueil
2018-02-01 15:31       ` [PATCH v7 00/14] JZ4770 and GCW0 patchset James Hogan
2018-01-05 18:25   ` [PATCH v6 02/15] clk: ingenic: Fix recalc_rate for clocks with fixed divider Paul Cercueil
2018-01-05 18:25   ` [PATCH v6 03/15] clk: ingenic: support PLLs with no bypass bit Paul Cercueil
2018-01-05 18:25   ` Paul Cercueil [this message]
2018-01-05 18:25   ` [PATCH v6 05/15] dt-bindings: clock: Add jz4770-cgu.h header Paul Cercueil
2018-01-05 18:25   ` [PATCH v6 06/15] clk: Add Ingenic jz4770 CGU driver Paul Cercueil
2018-01-10 21:37     ` James Hogan
2018-01-05 18:25   ` [PATCH v6 07/15] MIPS: Setup boot_command_line before plat_mem_setup Paul Cercueil
2018-01-05 18:25   ` [PATCH v6 08/15] MIPS: ingenic: Use common cmdline handling code Paul Cercueil
2018-01-10 22:16     ` James Hogan
2018-01-05 18:25   ` [PATCH v6 09/15] MIPS: platform: add machtype IDs for more Ingenic SoCs Paul Cercueil
2018-01-10 22:19     ` James Hogan
2018-01-05 18:25   ` [PATCH v6 10/15] MIPS: ingenic: Detect machtype from SoC compatible string Paul Cercueil
2018-01-10 22:27     ` James Hogan
2018-01-16 14:06       ` Paul Cercueil
2018-01-05 18:25   ` [PATCH v6 11/15] MIPS: ingenic: Initial JZ4770 support Paul Cercueil
2018-01-10 22:42     ` James Hogan
2018-01-05 18:25   ` [PATCH v6 12/15] MIPS: JZ4770: Work around config2 misreporting associativity Paul Cercueil
2018-01-10 22:52     ` James Hogan
2018-01-05 18:25   ` [PATCH v6 13/15] MIPS: JZ4770: Workaround for corrupted DMA transfers Paul Cercueil
2018-01-10 23:20     ` James Hogan
2018-01-16 14:10       ` Paul Cercueil
2018-01-05 18:25   ` [PATCH v6 14/15] devicetree/bindings: Add GCW vendor prefix Paul Cercueil
2018-01-05 18:25   ` [PATCH v6 15/15] MIPS: ingenic: Initial GCW Zero support Paul Cercueil
2018-01-07 16:18     ` Philippe Ombredanne
2018-01-10 22:59       ` Paul Cercueil
2018-01-23 10:31         ` Philippe Ombredanne

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