From: Chris Packham <chris.packham@alliedtelesis.co.nz>
To: linux@armlinux.org.uk, bp@alien8.de, jlu@pengutronix.de
Cc: Chris.Packham@alliedtelesis.co.nz,
thomas.petazzoni@free-electrons.com, kernel@pengutronix.de,
gregory.clement@free-electrons.com,
Chris Packham <chris.packham@alliedtelesis.co.nz>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4 5/8] ARM: l2x0: add marvell,ecc-enable property for aurora
Date: Fri, 12 Jan 2018 14:27:52 +1300 [thread overview]
Message-ID: <20180112012755.20495-6-chris.packham@alliedtelesis.co.nz> (raw)
In-Reply-To: <20180112012755.20495-1-chris.packham@alliedtelesis.co.nz>
The aurora cache on the Marvell Armada-XP SoC supports ECC protection
for the L2 data arrays. Add a "marvell,ecc-enable" device tree property
which can be used to enable this.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
[jlu@pengutronix.de: use aurora specific define AURORA_ACR_ECC_EN]
Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
---
Documentation/devicetree/bindings/arm/l2c2x0.txt | 2 ++
arch/arm/mm/cache-l2x0.c | 7 +++++++
2 files changed, 9 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.txt b/Documentation/devicetree/bindings/arm/l2c2x0.txt
index fbe6cb21f4cf..15a84f0ba9f1 100644
--- a/Documentation/devicetree/bindings/arm/l2c2x0.txt
+++ b/Documentation/devicetree/bindings/arm/l2c2x0.txt
@@ -76,6 +76,8 @@ Optional properties:
specified to indicate that such transforms are precluded.
- arm,parity-enable : enable parity checking on the L2 cache (L220 or PL310).
- arm,parity-disable : disable parity checking on the L2 cache (L220 or PL310).
+- marvell,ecc-enable : enable ECC protection on the L2 cache
+- marvell,ecc-disable : disable ECC protection on the L2 cache
- arm,outer-sync-disable : disable the outer sync operation on the L2 cache.
Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that
will randomly hang unless outer sync operations are disabled.
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index b70bee74750d..644f786e4fa9 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -1505,6 +1505,13 @@ static void __init aurora_of_parse(const struct device_node *np,
mask |= AURORA_ACR_FORCE_WRITE_POLICY_MASK;
}
+ if (of_property_read_bool(np, "marvell,ecc-enable")) {
+ mask |= AURORA_ACR_ECC_EN;
+ val |= AURORA_ACR_ECC_EN;
+ } else if (of_property_read_bool(np, "marvell,ecc-disable")) {
+ mask |= AURORA_ACR_ECC_EN;
+ }
+
if (of_property_read_bool(np, "arm,parity-enable")) {
mask |= AURORA_ACR_PARITY_EN;
val |= AURORA_ACR_PARITY_EN;
--
2.15.1
next prev parent reply other threads:[~2018-01-12 1:29 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20180112012755.20495-1-chris.packham@alliedtelesis.co.nz>
2018-01-12 1:27 ` [PATCH v4 1/8] ARM: l2c: move cache-aurora-l2.h to asm/hardware Chris Packham
2018-01-12 1:27 ` [PATCH v4 2/8] ARM: aurora-l2: add prefix to MAX_RANGE_SIZE Chris Packham
2018-01-12 1:27 ` [PATCH v4 3/8] ARM: aurora-l2: add defines for parity and ECC registers Chris Packham
2018-01-12 1:27 ` [PATCH v4 4/8] ARM: l2x0: support parity-enable/disable on aurora Chris Packham
2018-01-12 1:27 ` Chris Packham [this message]
2018-01-19 21:28 ` [PATCH v4 5/8] ARM: l2x0: add marvell,ecc-enable property for aurora Rob Herring
2018-01-12 1:27 ` [PATCH v4 6/8] EDAC: Add missing debugfs_create_x32 wrapper Chris Packham
2018-01-12 1:27 ` [PATCH v4 7/8] EDAC: Add driver for the Marvell Armada XP SDRAM and L2 cache ECC Chris Packham
2018-01-12 18:44 ` Borislav Petkov
2018-01-12 1:27 ` [PATCH v4 8/8] EDAC: armada_xp: Add support for more SoCs Chris Packham
2018-01-12 18:47 ` Borislav Petkov
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