From: Greentime Hu <green.hu@gmail.com>
To: greentime@andestech.com, linux-kernel@vger.kernel.org,
arnd@arndb.de, linux-arch@vger.kernel.org, tglx@linutronix.de,
jason@lakedaemon.net, marc.zyngier@arm.com, robh+dt@kernel.org,
netdev@vger.kernel.org, deanbo422@gmail.com,
devicetree@vger.kernel.org, viro@zeniv.linux.org.uk,
dhowells@redhat.com, will.deacon@arm.com,
daniel.lezcano@linaro.org, linux-serial@vger.kernel.org,
geert.uytterhoeven@gmail.com, linus.walleij@linaro.org,
mark.rutland@arm.com, greg@kroah.com, ren_guo@c-sky.com,
rdunlap@infradead.org, davem@davemloft.net, jonas@southpole.se,
stefan.kristiansson@saunalahti.fi, shorne@gmail.com
Cc: green.hu@gmail.com, Vincent Chen <vincentc@andestech.com>
Subject: [PATCH v6 23/36] nds32: L2 cache support
Date: Mon, 15 Jan 2018 13:53:31 +0800 [thread overview]
Message-ID: <37ba0ace68e4fbd60a8283c9d82423c0b094056e.1515766253.git.green.hu@gmail.com> (raw)
In-Reply-To: <cover.1515766253.git.green.hu@gmail.com>
In-Reply-To: <cover.1515766253.git.green.hu@gmail.com>
From: Greentime Hu <greentime@andestech.com>
This patch adds L2 cache support.
Signed-off-by: Vincent Chen <vincentc@andestech.com>
Signed-off-by: Greentime Hu <greentime@andestech.com>
---
arch/nds32/include/asm/l2_cache.h | 137 +++++++++++++++++++++++++++++++++++++
arch/nds32/kernel/atl2c.c | 64 +++++++++++++++++
2 files changed, 201 insertions(+)
create mode 100644 arch/nds32/include/asm/l2_cache.h
create mode 100644 arch/nds32/kernel/atl2c.c
diff --git a/arch/nds32/include/asm/l2_cache.h b/arch/nds32/include/asm/l2_cache.h
new file mode 100644
index 0000000..37dd5ef
--- /dev/null
+++ b/arch/nds32/include/asm/l2_cache.h
@@ -0,0 +1,137 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef L2_CACHE_H
+#define L2_CACHE_H
+
+/* CCTL_CMD_OP */
+#define L2_CA_CONF_OFF 0x0
+#define L2_IF_CONF_OFF 0x4
+#define L2CC_SETUP_OFF 0x8
+#define L2CC_PROT_OFF 0xC
+#define L2CC_CTRL_OFF 0x10
+#define L2_INT_EN_OFF 0x20
+#define L2_STA_OFF 0x24
+#define RDERR_ADDR_OFF 0x28
+#define WRERR_ADDR_OFF 0x2c
+#define EVDPTERR_ADDR_OFF 0x30
+#define IMPL3ERR_ADDR_OFF 0x34
+#define L2_CNT0_CTRL_OFF 0x40
+#define L2_EVNT_CNT0_OFF 0x44
+#define L2_CNT1_CTRL_OFF 0x48
+#define L2_EVNT_CNT1_OFF 0x4c
+#define L2_CCTL_CMD_OFF 0x60
+#define L2_CCTL_STATUS_OFF 0x64
+#define L2_LINE_TAG_OFF 0x68
+#define L2_LINE_DPT_OFF 0x70
+
+#define CCTL_CMD_L2_IX_INVAL 0x0
+#define CCTL_CMD_L2_PA_INVAL 0x1
+#define CCTL_CMD_L2_IX_WB 0x2
+#define CCTL_CMD_L2_PA_WB 0x3
+#define CCTL_CMD_L2_PA_WBINVAL 0x5
+#define CCTL_CMD_L2_SYNC 0xa
+
+/* CCTL_CMD_TYPE */
+#define CCTL_SINGLE_CMD 0
+#define CCTL_BLOCK_CMD 0x10
+#define CCTL_ALL_CMD 0x10
+
+/******************************************************************************
+ * L2_CA_CONF (Cache architecture configuration)
+ *****************************************************************************/
+#define L2_CA_CONF_offL2SET 0
+#define L2_CA_CONF_offL2WAY 4
+#define L2_CA_CONF_offL2CLSZ 8
+#define L2_CA_CONF_offL2DW 11
+#define L2_CA_CONF_offL2PT 14
+#define L2_CA_CONF_offL2VER 16
+
+#define L2_CA_CONF_mskL2SET (0xFUL << L2_CA_CONF_offL2SET)
+#define L2_CA_CONF_mskL2WAY (0xFUL << L2_CA_CONF_offL2WAY)
+#define L2_CA_CONF_mskL2CLSZ (0x7UL << L2_CA_CONF_offL2CLSZ)
+#define L2_CA_CONF_mskL2DW (0x7UL << L2_CA_CONF_offL2DW)
+#define L2_CA_CONF_mskL2PT (0x3UL << L2_CA_CONF_offL2PT)
+#define L2_CA_CONF_mskL2VER (0xFFFFUL << L2_CA_CONF_offL2VER)
+
+/******************************************************************************
+ * L2CC_SETUP (L2CC Setup register)
+ *****************************************************************************/
+#define L2CC_SETUP_offPART 0
+#define L2CC_SETUP_mskPART (0x3UL << L2CC_SETUP_offPART)
+#define L2CC_SETUP_offDDLATC 4
+#define L2CC_SETUP_mskDDLATC (0x3UL << L2CC_SETUP_offDDLATC)
+#define L2CC_SETUP_offTDLATC 8
+#define L2CC_SETUP_mskTDLATC (0x3UL << L2CC_SETUP_offTDLATC)
+
+/******************************************************************************
+ * L2CC_PROT (L2CC Protect register)
+ *****************************************************************************/
+#define L2CC_PROT_offMRWEN 31
+#define L2CC_PROT_mskMRWEN (0x1UL << L2CC_PROT_offMRWEN)
+
+/******************************************************************************
+ * L2_CCTL_STATUS_Mn (The L2CCTL command working status for Master n)
+ *****************************************************************************/
+#define L2CC_CTRL_offEN 31
+#define L2CC_CTRL_mskEN (0x1UL << L2CC_CTRL_offEN)
+
+/******************************************************************************
+ * L2_CCTL_STATUS_Mn (The L2CCTL command working status for Master n)
+ *****************************************************************************/
+#define L2_CCTL_STATUS_offCMD_COMP 31
+#define L2_CCTL_STATUS_mskCMD_COMP (0x1 << L2_CCTL_STATUS_offCMD_COMP)
+
+extern void __iomem *atl2c_base;
+#include <linux/smp.h>
+#include <asm/io.h>
+#include <asm/bitfield.h>
+
+#define L2C_R_REG(offset) readl(atl2c_base + offset)
+#define L2C_W_REG(offset, value) writel(value, atl2c_base + offset)
+
+#define L2_CMD_RDY() \
+ do{;}while((L2C_R_REG(L2_CCTL_STATUS_OFF) & L2_CCTL_STATUS_mskCMD_COMP) == 0)
+
+static inline unsigned long L2_CACHE_SET(void)
+{
+ return 64 << ((L2C_R_REG(L2_CA_CONF_OFF) & L2_CA_CONF_mskL2SET) >>
+ L2_CA_CONF_offL2SET);
+}
+
+static inline unsigned long L2_CACHE_WAY(void)
+{
+ return 1 +
+ ((L2C_R_REG(L2_CA_CONF_OFF) & L2_CA_CONF_mskL2WAY) >>
+ L2_CA_CONF_offL2WAY);
+}
+
+static inline unsigned long L2_CACHE_LINE_SIZE(void)
+{
+
+ return 4 << ((L2C_R_REG(L2_CA_CONF_OFF) & L2_CA_CONF_mskL2CLSZ) >>
+ L2_CA_CONF_offL2CLSZ);
+}
+
+static inline unsigned long GET_L2CC_CTRL_CPU(unsigned long cpu)
+{
+ if (cpu == smp_processor_id())
+ return L2C_R_REG(L2CC_CTRL_OFF);
+ return L2C_R_REG(L2CC_CTRL_OFF + (cpu << 8));
+}
+
+static inline void SET_L2CC_CTRL_CPU(unsigned long cpu, unsigned long val)
+{
+ if (cpu == smp_processor_id())
+ L2C_W_REG(L2CC_CTRL_OFF, val);
+ else
+ L2C_W_REG(L2CC_CTRL_OFF + (cpu << 8), val);
+}
+
+static inline unsigned long GET_L2CC_STATUS_CPU(unsigned long cpu)
+{
+ if (cpu == smp_processor_id())
+ return L2C_R_REG(L2_CCTL_STATUS_OFF);
+ return L2C_R_REG(L2_CCTL_STATUS_OFF + (cpu << 8));
+}
+#endif
diff --git a/arch/nds32/kernel/atl2c.c b/arch/nds32/kernel/atl2c.c
new file mode 100644
index 0000000..0c6d031
--- /dev/null
+++ b/arch/nds32/kernel/atl2c.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/compiler.h>
+#include <linux/of_address.h>
+#include <linux/of_fdt.h>
+#include <linux/of_platform.h>
+#include <asm/l2_cache.h>
+
+void __iomem *atl2c_base;
+static const struct of_device_id atl2c_ids[] __initconst = {
+ {.compatible = "andestech,atl2c",}
+};
+
+static int __init atl2c_of_init(void)
+{
+ struct device_node *np;
+ struct resource res;
+ unsigned long tmp = 0;
+ unsigned long l2set, l2way, l2clsz;
+
+ if (!(__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskL2C))
+ return -ENODEV;
+
+ np = of_find_matching_node(NULL, atl2c_ids);
+ if (!np)
+ return -ENODEV;
+
+ if (of_address_to_resource(np, 0, &res))
+ return -ENODEV;
+
+ atl2c_base = ioremap(res.start, resource_size(&res));
+ if (!atl2c_base)
+ return -ENOMEM;
+
+ l2set =
+ 64 << ((L2C_R_REG(L2_CA_CONF_OFF) & L2_CA_CONF_mskL2SET) >>
+ L2_CA_CONF_offL2SET);
+ l2way =
+ 1 +
+ ((L2C_R_REG(L2_CA_CONF_OFF) & L2_CA_CONF_mskL2WAY) >>
+ L2_CA_CONF_offL2WAY);
+ l2clsz =
+ 4 << ((L2C_R_REG(L2_CA_CONF_OFF) & L2_CA_CONF_mskL2CLSZ) >>
+ L2_CA_CONF_offL2CLSZ);
+ pr_info("L2:%luKB/%luS/%luW/%luB\n",
+ l2set * l2way * l2clsz / 1024, l2set, l2way, l2clsz);
+
+ tmp = L2C_R_REG(L2CC_PROT_OFF);
+ tmp &= ~L2CC_PROT_mskMRWEN;
+ L2C_W_REG(L2CC_PROT_OFF, tmp);
+
+ tmp = L2C_R_REG(L2CC_SETUP_OFF);
+ tmp &= ~L2CC_SETUP_mskPART;
+ L2C_W_REG(L2CC_SETUP_OFF, tmp);
+
+ tmp = L2C_R_REG(L2CC_CTRL_OFF);
+ tmp |= L2CC_CTRL_mskEN;
+ L2C_W_REG(L2CC_CTRL_OFF, tmp);
+
+ return 0;
+}
+
+subsys_initcall(atl2c_of_init);
--
1.7.9.5
next prev parent reply other threads:[~2018-01-15 5:56 UTC|newest]
Thread overview: 111+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-15 5:53 [PATCH v6 00/36] Andes(nds32) Linux Kernel Port Greentime Hu
2018-01-15 5:53 ` [PATCH v6 01/36] asm-generic/io.h: move ioremap_nocache/ioremap_uc/ioremap_wc/ioremap_wt out of ifndef CONFIG_MMU Greentime Hu
2018-01-15 5:53 ` [PATCH v6 02/36] openrisc: add ioremap_nocache declaration before include asm-generic/io.h and sync ioremap prototype with it Greentime Hu
2018-01-15 13:07 ` Stafford Horne
2018-01-15 13:28 ` Greentime Hu
2018-01-15 5:53 ` [PATCH v6 03/36] sparc: io: To use the define of ioremap_[nocache|wc|wb] in asm-generic/io.h Greentime Hu
2018-01-18 9:56 ` Arnd Bergmann
2018-01-19 12:50 ` Greentime Hu
2018-01-15 5:53 ` [PATCH v6 04/36] earlycon: add reg-offset to physical address before mapping Greentime Hu
2018-01-18 10:00 ` Arnd Bergmann
2018-01-15 5:53 ` [PATCH v6 05/36] nds32: Assembly macros and definitions Greentime Hu
2018-01-18 10:01 ` Arnd Bergmann
2018-01-15 5:53 ` [PATCH v6 06/36] nds32: Kernel booting and initialization Greentime Hu
2018-01-18 10:11 ` Arnd Bergmann
2018-01-19 16:34 ` Greentime Hu
2018-01-19 16:41 ` Arnd Bergmann
2018-01-22 9:49 ` Greentime Hu
2018-01-22 9:53 ` Arnd Bergmann
2018-01-15 5:53 ` [PATCH v6 07/36] nds32: Exception handling Greentime Hu
2018-01-18 10:14 ` Arnd Bergmann
2018-01-24 10:53 ` Vincent Chen
2018-01-24 11:09 ` Arnd Bergmann
2018-01-24 11:10 ` Arnd Bergmann
2018-01-30 10:01 ` Vincent Chen
2018-01-30 13:33 ` Arnd Bergmann
2018-01-30 14:49 ` Greentime Hu
2018-01-30 15:27 ` Arnd Bergmann
2018-01-15 5:53 ` [PATCH v6 08/36] nds32: MMU definitions Greentime Hu
2018-01-18 10:14 ` Arnd Bergmann
2018-01-15 5:53 ` [PATCH v6 09/36] nds32: MMU initialization Greentime Hu
2018-01-18 10:16 ` Arnd Bergmann
2018-01-15 5:53 ` [PATCH v6 10/36] nds32: MMU fault handling and page table management Greentime Hu
2018-01-18 10:16 ` Arnd Bergmann
2018-01-15 5:53 ` [PATCH v6 11/36] nds32: Cache and TLB routines Greentime Hu
2018-01-18 10:17 ` Arnd Bergmann
2018-01-15 5:53 ` [PATCH v6 12/36] nds32: Process management Greentime Hu
2018-01-18 10:22 ` Arnd Bergmann
2018-01-15 5:53 ` [PATCH v6 13/36] nds32: IRQ handling Greentime Hu
2018-01-18 10:22 ` Arnd Bergmann
2018-01-15 5:53 ` [PATCH v6 14/36] nds32: Atomic operations Greentime Hu
2018-01-18 10:23 ` Arnd Bergmann
2018-01-15 5:53 ` [PATCH v6 15/36] nds32: Device specific operations Greentime Hu
2018-01-18 10:25 ` Arnd Bergmann
2018-01-15 5:53 ` [PATCH v6 16/36] nds32: DMA mapping API Greentime Hu
2018-01-18 10:26 ` Arnd Bergmann
2018-01-23 8:23 ` Greentime Hu
2018-01-23 11:52 ` Greentime Hu
2018-01-24 11:36 ` Arnd Bergmann
2018-01-25 3:45 ` Greentime Hu
2018-01-25 10:42 ` Arnd Bergmann
2018-01-25 13:48 ` Greentime Hu
2018-01-15 5:53 ` [PATCH v6 17/36] nds32: ELF definitions Greentime Hu
2018-01-18 10:27 ` Arnd Bergmann
2018-01-15 5:53 ` [PATCH v6 18/36] nds32: System calls handling Greentime Hu
2018-01-18 10:27 ` Arnd Bergmann
2018-01-15 5:53 ` [PATCH v6 19/36] nds32: VDSO support Greentime Hu
2018-01-18 10:28 ` Arnd Bergmann
2018-02-06 7:41 ` Vincent Chen
2018-02-06 8:48 ` Arnd Bergmann
2018-01-15 5:53 ` [PATCH v6 20/36] nds32: Signal handling support Greentime Hu
2018-01-18 10:30 ` Arnd Bergmann
2018-01-24 0:56 ` Vincent Chen
2018-01-24 11:13 ` Arnd Bergmann
2018-02-06 6:39 ` Vincent Chen
2018-01-15 5:53 ` [PATCH v6 21/36] nds32: Library functions Greentime Hu
2018-01-18 10:31 ` Arnd Bergmann
2018-01-15 5:53 ` [PATCH v6 22/36] nds32: Debugging support Greentime Hu
2018-01-18 10:37 ` Arnd Bergmann
2018-01-23 7:28 ` Vincent Chen
2018-01-23 8:21 ` Arnd Bergmann
2018-01-15 5:53 ` Greentime Hu [this message]
2018-01-18 10:37 ` [PATCH v6 23/36] nds32: L2 cache support Arnd Bergmann
2018-01-15 5:53 ` [PATCH v6 24/36] nds32: Loadable modules Greentime Hu
2018-01-18 10:41 ` Arnd Bergmann
2018-01-19 14:26 ` Greentime Hu
2018-01-15 5:53 ` [PATCH v6 25/36] nds32: Generic timers support Greentime Hu
2018-01-18 10:41 ` Arnd Bergmann
2018-01-15 5:53 ` [PATCH v6 26/36] nds32: Device tree support Greentime Hu
2018-01-18 10:43 ` Arnd Bergmann
2018-01-15 5:53 ` [PATCH v6 27/36] nds32: Miscellaneous header files Greentime Hu
2018-01-18 10:46 ` Arnd Bergmann
2018-01-15 5:53 ` [PATCH v6 28/36] nds32: defconfig Greentime Hu
2018-01-18 10:44 ` Arnd Bergmann
2018-01-15 5:53 ` [PATCH v6 29/36] nds32: Build infrastructure Greentime Hu
2018-01-18 11:00 ` Arnd Bergmann
2018-01-22 15:20 ` Greentime Hu
2018-01-22 15:38 ` Arnd Bergmann
2018-01-22 16:00 ` Greentime Hu
2018-01-15 5:53 ` [PATCH v6 30/36] MAINTAINERS: Add nds32 Greentime Hu
2018-01-18 10:45 ` Arnd Bergmann
2018-01-15 5:53 ` [PATCH v6 31/36] dt-bindings: nds32 CPU Bindings Greentime Hu
2018-01-18 11:02 ` Arnd Bergmann
2018-01-19 14:32 ` Greentime Hu
2018-01-19 14:52 ` Arnd Bergmann
2018-01-19 15:18 ` Greentime Hu
2018-01-19 15:29 ` Geert Uytterhoeven
2018-01-19 15:35 ` Greentime Hu
2018-01-19 15:37 ` Geert Uytterhoeven
2018-01-22 9:53 ` Greentime Hu
2018-01-22 11:15 ` Arnd Bergmann
2018-01-22 13:55 ` Greentime Hu
2018-01-15 5:53 ` [PATCH v6 32/36] dt-bindings: nds32 L2 cache controller Bindings Greentime Hu
2018-01-18 10:45 ` Arnd Bergmann
2018-01-15 5:53 ` [PATCH v6 33/36] dt-bindings: nds32 SoC Bindings Greentime Hu
2018-01-18 11:03 ` Arnd Bergmann
2018-01-15 5:53 ` [PATCH v6 34/36] dt-bindings: interrupt-controller: Andestech Internal Vector Interrupt Controller Greentime Hu
2018-01-18 10:46 ` Arnd Bergmann
2018-01-15 5:53 ` [PATCH v6 35/36] irqchip: Andestech Internal Vector Interrupt Controller driver Greentime Hu
2018-01-15 5:53 ` [PATCH v6 36/36] net: faraday add nds32 support Greentime Hu
2018-01-18 11:02 ` Arnd Bergmann
2018-01-18 9:49 ` [PATCH v6 00/36] Andes(nds32) Linux Kernel Port Arnd Bergmann
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