From: Alexandre Belloni <alexandre.belloni@free-electrons.com>
To: James Hogan <jhogan@kernel.org>, Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org,
Alexandre Belloni <alexandre.belloni@free-electrons.com>,
Rob Herring <robh+dt@kernel.org>,
devicetree@vger.kernel.org
Subject: [PATCH v3 1/8] dt-bindings: mips: Add bindings for Microsemi SoCs
Date: Tue, 16 Jan 2018 11:12:33 +0100 [thread overview]
Message-ID: <20180116101240.5393-2-alexandre.belloni@free-electrons.com> (raw)
In-Reply-To: <20180116101240.5393-1-alexandre.belloni@free-electrons.com>
Add bindings for Microsemi SoCs. Currently only Ocelot is supported.
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
Documentation/devicetree/bindings/mips/mscc.txt | 44 +++++++++++++++++++++++++
1 file changed, 44 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mips/mscc.txt
diff --git a/Documentation/devicetree/bindings/mips/mscc.txt b/Documentation/devicetree/bindings/mips/mscc.txt
new file mode 100644
index 000000000000..f531d195efc5
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/mscc.txt
@@ -0,0 +1,44 @@
+* Microsemi MIPS CPUs
+
+Boards with a SoC of the Microsemi MIPS family shall have the following
+properties:
+
+Required properties:
+- compatible: "mscc,ocelot"
+- mips-hpt-frequency: CPU counter frequency.
+
+
+* Other peripherals:
+
+o CPU chip regs:
+
+The SoC has a few registers (DEVCPU_GCB:CHIP_REGS) handling miscellaneous
+functionalities: chip ID, general purpose register for software use, reset
+controller, hardware status and configuration, efuses.
+
+Required properties:
+- compatible: Should be "mscc,ocelot-chip-regs", "simple-mfd", "syscon"
+- reg : Should contain registers location and length
+
+Example:
+ syscon@71070000 {
+ compatible = "mscc,ocelot-chip-regs", "simple-mfd", "syscon";
+ reg = <0x71070000 0x1c>;
+ };
+
+
+o CPU system control:
+
+The SoC has a few registers (ICPU_CFG:CPU_SYSTEM_CTRL) handling configuration of
+the CPU: 8 general purpose registers, reset control, CPU en/disabling, CPU
+endianess, CPU bus control, CPU status.
+
+Required properties:
+- compatible: Should be "mscc,ocelot-cpu-syscon", "syscon"
+- reg : Should contain registers location and length
+
+Example:
+ syscon@70000000 {
+ compatible = "mscc,ocelot-cpu-syscon", "syscon";
+ reg = <0x70000000 0x2c>;
+ };
--
2.15.1
next prev parent reply other threads:[~2018-01-16 10:15 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-16 10:12 [PATCH v3 0/8] MIPS: add support for the Microsemi MIPS SoCs Alexandre Belloni
2018-01-16 10:12 ` Alexandre Belloni [this message]
2018-01-19 19:23 ` [PATCH v3 1/8] dt-bindings: mips: Add bindings for Microsemi SoCs Rob Herring
2018-02-14 16:38 ` James Hogan
2018-01-16 10:12 ` [PATCH v3 2/8] dt-bindings: power: reset: Document ocelot-reset binding Alexandre Belloni
2018-01-20 0:34 ` Rob Herring
2018-02-08 22:32 ` Sebastian Reichel
2018-01-16 10:12 ` [PATCH v3 3/8] power: reset: Add a driver for the Microsemi Ocelot reset Alexandre Belloni
2018-02-08 22:32 ` Sebastian Reichel
2018-01-16 10:12 ` [PATCH v3 4/8] MIPS: mscc: Add initial support for Microsemi MIPS SoCs Alexandre Belloni
2018-02-14 16:51 ` James Hogan
2018-02-14 21:38 ` Philippe Ombredanne
2018-01-16 10:12 ` [PATCH v3 5/8] MIPS: mscc: add ocelot dtsi Alexandre Belloni
2018-02-14 16:57 ` James Hogan
2018-02-27 15:47 ` Alexandre Belloni
2018-02-27 21:01 ` Jonas Gorski
2018-02-28 13:14 ` Alexandre Belloni
2018-01-16 10:12 ` [PATCH v3 6/8] MIPS: mscc: add ocelot PCB123 device tree Alexandre Belloni
2018-02-14 17:00 ` James Hogan
2018-02-27 15:54 ` Alexandre Belloni
2018-02-27 15:57 ` James Hogan
2018-01-16 10:12 ` [PATCH v3 7/8] MIPS: defconfigs: add a defconfig for Microsemi SoCs Alexandre Belloni
2018-02-14 17:03 ` James Hogan
2018-02-27 16:15 ` Alexandre Belloni
2018-02-27 16:23 ` James Hogan
2018-01-16 10:12 ` [PATCH v3 8/8] MAINTAINERS: Add entry for Microsemi MIPS SoCs Alexandre Belloni
2018-02-14 17:05 ` James Hogan
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20180116101240.5393-2-alexandre.belloni@free-electrons.com \
--to=alexandre.belloni@free-electrons.com \
--cc=devicetree@vger.kernel.org \
--cc=jhogan@kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mips@linux-mips.org \
--cc=ralf@linux-mips.org \
--cc=robh+dt@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).