From: David Woodhouse <dwmw@amazon.co.uk>
To: arjan@linux.intel.com, tglx@linutronix.de, karahmed@amazon.de,
x86@kernel.org, linux-kernel@vger.kernel.org,
tim.c.chen@linux.intel.com, bp@alien8.de, peterz@infradead.org,
pbonzini@redhat.com, ak@linux.intel.com,
torvalds@linux-foundation.org, gregkh@linux-foundation.org
Subject: [PATCH 2/4] x86/cpufeatures: Add AMD feature bits for Prediction Command
Date: Sat, 20 Jan 2018 12:03:31 +0000 [thread overview]
Message-ID: <1516449813-7654-3-git-send-email-dwmw@amazon.co.uk> (raw)
In-Reply-To: <1516449813-7654-1-git-send-email-dwmw@amazon.co.uk>
AMD doesn't implement the Speculation Control MSR that Intel does, but
the Prediction Control MSR does exist and is advertised by a separate
CPUID bit. Add support for that.
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
---
arch/x86/include/asm/cpufeatures.h | 1 +
arch/x86/kernel/cpu/scattered.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index adebdaa..624d978 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -207,6 +207,7 @@
#define X86_FEATURE_RETPOLINE_AMD ( 7*32+13) /* AMD Retpoline mitigation for Spectre variant 2 */
#define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor Inventory Number */
+#define X86_FEATURE_AMD_PRED_CMD ( 7*32+17) /* Prediction Command MSR (AMD) */
#define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth Allocation */
#define X86_FEATURE_RSB_CTXSW ( 7*32+19) /* Fill RSB on context switches */
diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
index df11f5d..c76009e 100644
--- a/arch/x86/kernel/cpu/scattered.c
+++ b/arch/x86/kernel/cpu/scattered.c
@@ -28,6 +28,7 @@ static const struct cpuid_bit cpuid_bits[] = {
{ X86_FEATURE_HW_PSTATE, CPUID_EDX, 7, 0x80000007, 0 },
{ X86_FEATURE_CPB, CPUID_EDX, 9, 0x80000007, 0 },
{ X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 },
+ { X86_FEATURE_AMD_PRED_CMD, CPUID_EDX, 12, 0x80000007, 0 },
{ X86_FEATURE_SME, CPUID_EAX, 0, 0x8000001f, 0 },
{ 0, 0, 0, 0, 0 }
};
--
2.7.4
next prev parent reply other threads:[~2018-01-20 12:03 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-20 12:03 [PATCH 0/4] Basic Speculation Control feature support David Woodhouse
2018-01-20 12:03 ` [PATCH 1/4] x86/cpufeatures: Add Intel feature bits for Speculation Control David Woodhouse
2018-01-20 20:29 ` Borislav Petkov
2018-01-20 21:51 ` Steven Noonan
2018-01-20 21:57 ` David Woodhouse
2018-01-20 12:03 ` David Woodhouse [this message]
2018-01-21 12:16 ` [PATCH 2/4] x86/cpufeatures: Add AMD feature bits for Prediction Command Borislav Petkov
2018-01-21 12:22 ` David Woodhouse
2018-01-21 12:34 ` Borislav Petkov
2018-01-21 12:41 ` David Woodhouse
2018-01-21 17:36 ` Tom Lendacky
2018-01-21 17:51 ` Borislav Petkov
2018-01-20 12:03 ` [PATCH 3/4] x86/msr: Add definitions for new speculation control MSRs David Woodhouse
2018-01-20 12:03 ` [PATCH 4/4] x86/pti: Do not enable PTI on fixed Intel processors David Woodhouse
2018-01-20 20:08 ` Thomas Gleixner
2018-01-20 20:13 ` Thomas Gleixner
2018-01-20 20:13 ` Woodhouse, David
2018-01-20 20:13 ` Woodhouse, David
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