From: Jerome Brunet <jbrunet@baylibre.com>
To: Neil Armstrong <narmstrong@baylibre.com>
Cc: Jerome Brunet <jbrunet@baylibre.com>,
Kevin Hilman <khilman@baylibre.com>,
Carlo Caione <carlo@caione.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@codeaurora.org>,
linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: [PATCH v2 6/9] clk: meson: add the gxl hdmi pll
Date: Fri, 19 Jan 2018 16:55:26 +0100 [thread overview]
Message-ID: <20180119155529.11532-7-jbrunet@baylibre.com> (raw)
In-Reply-To: <20180119155529.11532-1-jbrunet@baylibre.com>
The hdmi pll used in the gxl family is actually different from the gxbb
one. The register layout is completely different, which explain why the
hdmi pll rate has always been rubbish on the gxl family.
Adding the correct register field is the first part of the fix to get a
correct rate out the hdmi pll
Fixes: 0d48fc558d01 ("clk: meson-gxbb: Add GXL/GXM GP0 Variant")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
drivers/clk/meson/gxbb.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 48 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index cf083a1906d1..f74ed52e2673 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -253,6 +253,52 @@ static struct meson_clk_pll gxbb_hdmi_pll = {
},
};
+static struct meson_clk_pll gxl_hdmi_pll = {
+ .m = {
+ .reg_off = HHI_HDMI_PLL_CNTL,
+ .shift = 0,
+ .width = 9,
+ },
+ .n = {
+ .reg_off = HHI_HDMI_PLL_CNTL,
+ .shift = 9,
+ .width = 5,
+ },
+ .frac = {
+ /*
+ * On gxl, there is a register shift due to HHI_HDMI_PLL_CNTL1
+ * which does not exist on gxbb, so we compute the register
+ * offset based on the PLL base to get it right
+ */
+ .reg_off = HHI_HDMI_PLL_CNTL + 4,
+ .shift = 0,
+ .width = 12,
+ },
+ .od = {
+ .reg_off = HHI_HDMI_PLL_CNTL + 8,
+ .shift = 21,
+ .width = 2,
+ },
+ .od2 = {
+ .reg_off = HHI_HDMI_PLL_CNTL + 8,
+ .shift = 23,
+ .width = 2,
+ },
+ .od3 = {
+ .reg_off = HHI_HDMI_PLL_CNTL + 8,
+ .shift = 19,
+ .width = 2,
+ },
+ .lock = &meson_clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "hdmi_pll",
+ .ops = &meson_clk_pll_ro_ops,
+ .parent_names = (const char *[]){ "xtal" },
+ .num_parents = 1,
+ .flags = CLK_GET_RATE_NOCACHE,
+ },
+};
+
static struct meson_clk_pll gxbb_sys_pll = {
.m = {
.reg_off = HHI_SYS_PLL_CNTL,
@@ -1520,7 +1566,7 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
static struct clk_hw_onecell_data gxl_hw_onecell_data = {
.hws = {
[CLKID_SYS_PLL] = &gxbb_sys_pll.hw,
- [CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw,
+ [CLKID_HDMI_PLL] = &gxl_hdmi_pll.hw,
[CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw,
[CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw,
[CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw,
@@ -1675,7 +1721,7 @@ static struct meson_clk_pll *const gxbb_clk_plls[] = {
static struct meson_clk_pll *const gxl_clk_plls[] = {
&gxbb_fixed_pll,
- &gxbb_hdmi_pll,
+ &gxl_hdmi_pll,
&gxbb_sys_pll,
&gxl_gp0_pll,
};
--
2.14.3
next prev parent reply other threads:[~2018-01-19 15:56 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-19 15:55 [PATCH v2 0/9] clk: meson: pll fixes Jerome Brunet
2018-01-19 15:55 ` [PATCH v2 1/9] clk: meson: check pll rate param table before using it Jerome Brunet
2018-01-19 15:55 ` [PATCH v2 2/9] clk: meson: remove useless pll rate params tables Jerome Brunet
2018-01-19 15:55 ` [PATCH v2 3/9] clk: meson: remove unnecessary rounding in the pll clock Jerome Brunet
2018-01-19 15:55 ` [PATCH v2 4/9] clk: meson: use the frac parameter width instead of a constant Jerome Brunet
2018-01-19 15:55 ` [PATCH v2 5/9] clk: meson: add od3 to the pll driver Jerome Brunet
2018-01-19 15:55 ` Jerome Brunet [this message]
2018-01-19 15:55 ` [PATCH v2 7/9] clk: meson: fix rate calculation of plls with a fractional part Jerome Brunet
2018-01-19 15:55 ` [PATCH v2 8/9] clk: meson: gxbb: add the fractional part of the fixed_pll Jerome Brunet
2018-01-19 15:55 ` [PATCH v2 9/9] clk: meson: axg: " Jerome Brunet
2018-01-30 19:10 ` [PATCH v2 0/9] clk: meson: pll fixes Jerome Brunet
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