linux-kernel.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Abhishek Sahu <absahu@codeaurora.org>
To: Boris Brezillon <boris.brezillon@bootlin.com>,
	Miquel Raynal <miquel.raynal@bootlin.com>
Cc: David Woodhouse <dwmw2@infradead.org>,
	Brian Norris <computersforpeace@gmail.com>,
	Marek Vasut <marek.vasut@gmail.com>,
	Richard Weinberger <richard@nod.at>,
	linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-mtd@lists.infradead.org, Andy Gross <andy.gross@linaro.org>,
	Archit Taneja <architt@codeaurora.org>,
	Abhishek Sahu <absahu@codeaurora.org>,
	Masahiro Yamada <yamada.masahiro@socionext.com>
Subject: [PATCH v4 01/15] mtd: rawnand: helper function for setting up ECC configuration
Date: Wed, 20 Jun 2018 12:57:28 +0530	[thread overview]
Message-ID: <1529479662-4026-2-git-send-email-absahu@codeaurora.org> (raw)
In-Reply-To: <1529479662-4026-1-git-send-email-absahu@codeaurora.org>

commit 2c8f8afa7f92 ("mtd: nand: add generic helpers to check,
match, maximize ECC settings") provides generic helpers which
drivers can use for setting up ECC parameters.

Since same board can have different ECC strength nand chips so
following is the logic for setting up ECC strength and ECC step
size, which can be used by most of the drivers.

1. If both ECC step size and ECC strength are already set
   (usually by DT) then just check whether this setting
   is supported by NAND controller.
2. If NAND_ECC_MAXIMIZE is set, then select maximum ECC strength
   supported by NAND controller.
3. Otherwise, try to match the ECC step size and ECC strength closest
   to the chip's requirement. If available OOB size can't fit the chip
   requirement then select maximum ECC strength which can be fit with
   available OOB size.

This patch introduces nand_ecc_choose_conf function which calls the
required helper functions for the above logic. The drivers can use
this single function instead of calling the 3 helper functions
individually.

CC: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
* Changes from v3:
  1. call nand_maximize_ecc() 2 times to make code more clear.

* Changes from v2:

  1. Renamed function to nand_ecc_choose_conf.
  2. Minor code reorganization to remove warning and 2 function calls
     for nand_maximize_ecc.

* Changes from v1:
  NEW PATCH

 drivers/mtd/nand/raw/nand_base.c | 33 +++++++++++++++++++++++++++++++++
 include/linux/mtd/rawnand.h      |  3 +++
 2 files changed, 36 insertions(+)

diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index 10c4f991..c64e3fc 100644
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -6287,6 +6287,39 @@ int nand_maximize_ecc(struct nand_chip *chip,
 }
 EXPORT_SYMBOL_GPL(nand_maximize_ecc);
 
+/**
+ * nand_ecc_choose_conf - Set the ECC strength and ECC step size
+ * @chip: nand chip info structure
+ * @caps: ECC engine caps info structure
+ * @oobavail: OOB size that the ECC engine can use
+ *
+ * Choose the ECC configuration according to following logic
+ *
+ * 1. If both ECC step size and ECC strength are already set (usually by DT)
+ *    then check if it is supported by this controller.
+ * 2. If NAND_ECC_MAXIMIZE is set, then select maximum ECC strength.
+ * 3. Otherwise, try to match the ECC step size and ECC strength closest
+ *    to the chip's requirement. If available OOB size can't fit the chip
+ *    requirement then fallback to the maximum ECC step size and ECC strength.
+ *
+ * On success, the chosen ECC settings are set.
+ */
+int nand_ecc_choose_conf(struct nand_chip *chip,
+			 const struct nand_ecc_caps *caps, int oobavail)
+{
+	if (chip->ecc.size && chip->ecc.strength)
+		return nand_check_ecc_caps(chip, caps, oobavail);
+
+	if (chip->ecc.options & NAND_ECC_MAXIMIZE)
+		return nand_maximize_ecc(chip, caps, oobavail);
+
+	if (!nand_match_ecc_req(chip, caps, oobavail))
+		return 0;
+
+	return nand_maximize_ecc(chip, caps, oobavail);
+}
+EXPORT_SYMBOL_GPL(nand_ecc_choose_conf);
+
 /*
  * Check if the chip configuration meet the datasheet requirements.
 
diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h
index 3e8ec3b..03a0061 100644
--- a/include/linux/mtd/rawnand.h
+++ b/include/linux/mtd/rawnand.h
@@ -1650,6 +1650,9 @@ int nand_match_ecc_req(struct nand_chip *chip,
 int nand_maximize_ecc(struct nand_chip *chip,
 		      const struct nand_ecc_caps *caps, int oobavail);
 
+int nand_ecc_choose_conf(struct nand_chip *chip,
+			 const struct nand_ecc_caps *caps, int oobavail);
+
 /* Default write_oob implementation */
 int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page);
 
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc.
is a member of Code Aurora Forum, hosted by The Linux Foundation


  reply	other threads:[~2018-06-20  8:52 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-20  7:27 [PATCH v4 00/15] Update for QCOM NAND driver Abhishek Sahu
2018-06-20  7:27 ` Abhishek Sahu [this message]
2018-06-25  2:23   ` [PATCH v4 01/15] mtd: rawnand: helper function for setting up ECC configuration Masahiro Yamada
2018-06-20  7:27 ` [PATCH v4 02/15] mtd: rawnand: denali: use helper function for ecc setup Abhishek Sahu
2018-06-20  7:27 ` [PATCH v4 03/15] dt-bindings: qcom_nandc: update for ECC strength and step size Abhishek Sahu
2018-06-20 16:01   ` Rob Herring
2018-06-20  7:27 ` [PATCH v4 04/15] mtd: rawnand: qcom: remove dt property nand-ecc-step-size Abhishek Sahu
2018-06-20  7:27 ` [PATCH v4 05/15] mtd: rawnand: qcom: use the ecc strength from device parameter Abhishek Sahu
2018-06-20  7:27 ` [PATCH v4 06/15] mtd: rawnand: qcom: wait for desc completion in all BAM channels Abhishek Sahu
2018-06-20  7:27 ` [PATCH v4 07/15] mtd: rawnand: qcom: erased page detection for uncorrectable errors only Abhishek Sahu
2018-06-20  7:27 ` [PATCH v4 08/15] mtd: rawnand: qcom: fix null pointer access for erased page detection Abhishek Sahu
2018-06-20  7:27 ` [PATCH v4 09/15] mtd: rawnand: qcom: parse read errors for read oob also Abhishek Sahu
2018-06-20  7:27 ` [PATCH v4 10/15] mtd: rawnand: qcom: modify write_oob to remove read codeword part Abhishek Sahu
2018-06-20  7:27 ` [PATCH v4 11/15] mtd: rawnand: qcom: fix return value for raw page read Abhishek Sahu
2018-06-20  7:27 ` [PATCH v4 12/15] mtd: rawnand: qcom: check for operation errors in case of raw read Abhishek Sahu
2018-06-20  7:27 ` [PATCH v4 13/15] mtd: rawnand: qcom: code reorganization for " Abhishek Sahu
2018-06-20  7:27 ` [PATCH v4 14/15] mtd: rawnand: qcom: erased page bitflips detection Abhishek Sahu
2018-06-26 18:02   ` Miquel Raynal
2018-06-20  7:27 ` [PATCH v4 15/15] mtd: rawnand: provide only single helper function for ECC conf Abhishek Sahu
2018-07-01 18:09 ` [PATCH v4 00/15] Update for QCOM NAND driver Miquel Raynal
2018-07-03  3:30   ` Abhishek Sahu

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1529479662-4026-2-git-send-email-absahu@codeaurora.org \
    --to=absahu@codeaurora.org \
    --cc=andy.gross@linaro.org \
    --cc=architt@codeaurora.org \
    --cc=boris.brezillon@bootlin.com \
    --cc=computersforpeace@gmail.com \
    --cc=dwmw2@infradead.org \
    --cc=linux-arm-msm@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-mtd@lists.infradead.org \
    --cc=marek.vasut@gmail.com \
    --cc=miquel.raynal@bootlin.com \
    --cc=richard@nod.at \
    --cc=yamada.masahiro@socionext.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).