From: Esben Haabendal <esben.haabendal@gmail.com>
To: Mark Brown <broonie@kernel.org>, linux-spi@vger.kernel.org
Cc: "Kurt Kanzenbach" <kurt@linutronix.de>,
"Angelo Dureghello" <angelo@sysam.it>,
"Nikita Yushchenko" <nikita.yoush@cogentembedded.com>,
"Sanchayan Maity" <maitysanchayan@gmail.com>,
"Yuan Yao" <yao.yuan@nxp.com>,
linux-kernel@vger.kernel.org, "Esben Haabendal" <eha@deif.com>,
"Martin Hundebøll" <martin@geanix.com>
Subject: [PATCH 06/12] spi: spi-fsl-dspi: Fixup regmap configuration
Date: Wed, 20 Jun 2018 09:34:36 +0200 [thread overview]
Message-ID: <20180620073442.20913-7-esben.haabendal@gmail.com> (raw)
In-Reply-To: <20180620073442.20913-1-esben.haabendal@gmail.com>
From: Esben Haabendal <eha@deif.com>
Mark volatile registers to avoid caching bugs.
Note: SPI_MCR is marked volatile because of CLR_TXF and CLR_RXF bits.
Signed-off-by: Esben Haabendal <eha@deif.com>
Cc: Martin Hundebøll <martin@geanix.com>
---
drivers/spi/spi-fsl-dspi.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c
index df07dd4722fb..5c5905b6509f 100644
--- a/drivers/spi/spi-fsl-dspi.c
+++ b/drivers/spi/spi-fsl-dspi.c
@@ -862,11 +862,23 @@ static int dspi_resume(struct device *dev)
static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume);
+static const struct regmap_range dspi_volatile_ranges[] = {
+ regmap_reg_range(SPI_MCR, SPI_TCR),
+ regmap_reg_range(SPI_SR, SPI_SR),
+ regmap_reg_range(SPI_PUSHR, SPI_RXFR3),
+};
+
+static const struct regmap_access_table dspi_volatile_table = {
+ .yes_ranges = dspi_volatile_ranges,
+ .n_yes_ranges = ARRAY_SIZE(dspi_volatile_ranges),
+};
+
static const struct regmap_config dspi_regmap_config = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.max_register = 0x88,
+ .volatile_table = &dspi_volatile_table,
};
static void dspi_init(struct fsl_dspi *dspi)
--
2.17.1
next prev parent reply other threads:[~2018-06-20 8:38 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-20 7:34 [PATCH 00/12] XSPI mode for LS1021A DSPI Esben Haabendal
2018-06-20 7:34 ` [PATCH 01/12] spi: spi-fsl-dspi: Drop unreachable else if statement Esben Haabendal
2018-06-20 8:40 ` Martin Hundebøll
2018-06-20 7:34 ` [PATCH 02/12] spi: spi-fsl-dspi: Drop unneeded use of dataflags bits Esben Haabendal
2018-06-20 7:34 ` [PATCH 03/12] spi: spi-fsl-dspi: Fix per transfer cs_change handling Esben Haabendal
2018-06-20 13:27 ` Mark Brown
2018-06-20 13:40 ` Esben Haabendal
2018-06-20 7:34 ` [PATCH 04/12] spi: spi-fsl-dspi: Simplify transfer counter handling Esben Haabendal
2018-06-20 7:34 ` [PATCH 05/12] spi: spi-fsl-dspi: Support 4 to 16 bits per word transfers Esben Haabendal
2018-06-20 7:34 ` Esben Haabendal [this message]
2018-06-20 7:34 ` [PATCH 07/12] spi: spi-fsl-dspi: Fix MCR register handling Esben Haabendal
2018-06-20 7:34 ` [PATCH 08/12] spi: spi-fsl-dspi: Add support for XSPI mode registers Esben Haabendal
2018-06-20 7:34 ` [PATCH 09/12] spi: spi-fsl-dspi: Framesize control for XSPI mode Esben Haabendal
2018-06-20 7:34 ` [PATCH 10/12] spi: spi-fsl-dspi: XSPI FIFO handling (in TCFQ mode) Esben Haabendal
2018-06-20 7:34 ` [PATCH 11/12] spi: spi-fsl-dspi: Advertise 32 bit for XSPI mode Esben Haabendal
2018-06-20 7:34 ` [PATCH 12/12] spi: spi-fsl-dspi: Enable extended SPI mode Esben Haabendal
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