From: Esben Haabendal <esben.haabendal@gmail.com>
To: Mark Brown <broonie@kernel.org>, linux-spi@vger.kernel.org
Cc: "Kurt Kanzenbach" <kurt@linutronix.de>,
"Angelo Dureghello" <angelo@sysam.it>,
"Nikita Yushchenko" <nikita.yoush@cogentembedded.com>,
"Sanchayan Maity" <maitysanchayan@gmail.com>,
"Yuan Yao" <yao.yuan@nxp.com>,
linux-kernel@vger.kernel.org, "Esben Haabendal" <eha@deif.com>,
"Martin Hundebøll" <martin@geanix.com>
Subject: [PATCH 09/12] spi: spi-fsl-dspi: Framesize control for XSPI mode
Date: Wed, 20 Jun 2018 09:34:39 +0200 [thread overview]
Message-ID: <20180620073442.20913-10-esben.haabendal@gmail.com> (raw)
In-Reply-To: <20180620073442.20913-1-esben.haabendal@gmail.com>
From: Esben Haabendal <eha@deif.com>
Signed-off-by: Esben Haabendal <eha@deif.com>
Cc: Martin Hundebøll <martin@geanix.com>
---
drivers/spi/spi-fsl-dspi.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c
index 3e9dd645ee54..ba83ff4512c9 100644
--- a/drivers/spi/spi-fsl-dspi.c
+++ b/drivers/spi/spi-fsl-dspi.c
@@ -119,6 +119,9 @@
#define SPI_FRAME_BITS_16 SPI_CTAR_FMSZ(0xf)
#define SPI_FRAME_BITS_8 SPI_CTAR_FMSZ(0x7)
+#define SPI_FRAME_EBITS(bits) SPI_CTARE_FMSZE(((bits) - 1) >> 4)
+#define SPI_FRAME_EBITS_MASK SPI_CTARE_FMSZE(1)
+
/* Register offsets for regmap_pushr */
#define PUSHR_CMD 0x0
#define PUSHR_TX 0x2
@@ -662,6 +665,10 @@ static int dspi_transfer_one_message(struct spi_master *master,
regmap_write(dspi->regmap, SPI_CTAR(0),
dspi->cur_chip->ctar_val |
SPI_FRAME_BITS(transfer->bits_per_word));
+ if (dspi->devtype_data->xspi_mode)
+ regmap_write(dspi->regmap, SPI_CTARE(0),
+ SPI_FRAME_EBITS(transfer->bits_per_word)
+ | SPI_CTARE_DTCP(1));
trans_mode = dspi->devtype_data->trans_mode;
switch (trans_mode) {
@@ -922,6 +929,9 @@ static void dspi_init(struct fsl_dspi *dspi)
{
regmap_write(dspi->regmap, SPI_MCR, SPI_MCR_MASTER | SPI_MCR_PCSIS);
regmap_write(dspi->regmap, SPI_SR, SPI_SR_CLEAR);
+ if (dspi->devtype_data->xspi_mode)
+ regmap_write(dspi->regmap, SPI_CTARE(0),
+ SPI_CTARE_FMSZE(0) | SPI_CTARE_DTCP(1));
}
static int dspi_probe(struct platform_device *pdev)
--
2.17.1
next prev parent reply other threads:[~2018-06-20 8:37 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-20 7:34 [PATCH 00/12] XSPI mode for LS1021A DSPI Esben Haabendal
2018-06-20 7:34 ` [PATCH 01/12] spi: spi-fsl-dspi: Drop unreachable else if statement Esben Haabendal
2018-06-20 8:40 ` Martin Hundebøll
2018-06-20 7:34 ` [PATCH 02/12] spi: spi-fsl-dspi: Drop unneeded use of dataflags bits Esben Haabendal
2018-06-20 7:34 ` [PATCH 03/12] spi: spi-fsl-dspi: Fix per transfer cs_change handling Esben Haabendal
2018-06-20 13:27 ` Mark Brown
2018-06-20 13:40 ` Esben Haabendal
2018-06-20 7:34 ` [PATCH 04/12] spi: spi-fsl-dspi: Simplify transfer counter handling Esben Haabendal
2018-06-20 7:34 ` [PATCH 05/12] spi: spi-fsl-dspi: Support 4 to 16 bits per word transfers Esben Haabendal
2018-06-20 7:34 ` [PATCH 06/12] spi: spi-fsl-dspi: Fixup regmap configuration Esben Haabendal
2018-06-20 7:34 ` [PATCH 07/12] spi: spi-fsl-dspi: Fix MCR register handling Esben Haabendal
2018-06-20 7:34 ` [PATCH 08/12] spi: spi-fsl-dspi: Add support for XSPI mode registers Esben Haabendal
2018-06-20 7:34 ` Esben Haabendal [this message]
2018-06-20 7:34 ` [PATCH 10/12] spi: spi-fsl-dspi: XSPI FIFO handling (in TCFQ mode) Esben Haabendal
2018-06-20 7:34 ` [PATCH 11/12] spi: spi-fsl-dspi: Advertise 32 bit for XSPI mode Esben Haabendal
2018-06-20 7:34 ` [PATCH 12/12] spi: spi-fsl-dspi: Enable extended SPI mode Esben Haabendal
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