From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org, mathieu.poirier@linaro.org,
robh@kernel.org, frowand.list@gmail.com,
devicetree@vger.kernel.org,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Mark Rutland <mark.rutland@arm.com>
Subject: [PATCH v2 4/6] dts: bindings: Document device tree binding for CATU
Date: Mon, 25 Jun 2018 12:22:11 +0100 [thread overview]
Message-ID: <20180625112213.23492-5-suzuki.poulose@arm.com> (raw)
In-Reply-To: <20180625112213.23492-1-suzuki.poulose@arm.com>
Document CATU device-tree bindings. CATU augments the TMC-ETR
by providing an improved Scatter Gather mechanism for streaming
trace data to non-contiguous system RAM pages.
Cc: devicetree@vger.kernel.org
Cc: frowand.list@gmail.com
Cc: Rob Herring <robh@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
.../devicetree/bindings/arm/coresight.txt | 53 ++++++++++++++++++++++
1 file changed, 53 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt
index 9aa30a1..5d1ad09 100644
--- a/Documentation/devicetree/bindings/arm/coresight.txt
+++ b/Documentation/devicetree/bindings/arm/coresight.txt
@@ -39,6 +39,8 @@ its hardware characteristcs.
- System Trace Macrocell:
"arm,coresight-stm", "arm,primecell"; [1]
+ - Coresight Address Translation Unit (CATU)
+ "arm,coresight-catu", "arm,primecell";
* reg: physical base address and length of the register
set(s) of the component.
@@ -90,6 +92,10 @@ its hardware characteristcs.
* arm,scatter-gather: boolean. Indicates that the TMC-ETR can safely
use the SG mode on this system.
+* Optional property for CATU :
+ * interrupts : Exactly one SPI may be listed for reporting the address
+ error
+
Example:
1. Sinks
@@ -121,6 +127,35 @@ Example:
};
};
+ etr@20070000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0 0x20070000 0 0x1000>;
+
+ clocks = <&oscclk6a>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* input port */
+ port@0 {
+ reg = <0>;
+ etr_in_port: endpoint {
+ slave-mode;
+ remote-endpoint = <&replicator2_out_port0>;
+ };
+ };
+
+ /* CATU link represented by output port */
+ port@1 {
+ reg = <1>;
+ etr_out_port: endpoint {
+ remote-endpoint = <&catu_in_port>;
+ };
+ };
+ };
+ };
+
2. Links
replicator {
/* non-configurable replicators don't show up on the
@@ -250,5 +285,23 @@ Example:
};
};
+5. CATU
+
+ catu@207e0000 {
+ compatible = "arm,coresight-catu", "arm,primecell";
+ reg = <0 0x207e0000 0 0x1000>;
+
+ clocks = <&oscclk6a>;
+ clock-names = "apb_pclk";
+
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ port {
+ catu_in_port: endpoint {
+ slave-mode;
+ remote-endpoint = <&etr_out_port>;
+ };
+ };
+ };
+
[1]. There is currently two version of STM: STM32 and STM500. Both
have the same HW interface and as such don't need an explicit binding name.
--
2.9.5
next prev parent reply other threads:[~2018-06-25 11:23 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-25 11:22 [PATCH v2 0/6] coresight: Coresight Address Translation Unit support Suzuki K Poulose
2018-06-25 11:22 ` [PATCH v2 1/6] coresight: Cleanup device subtype struct Suzuki K Poulose
2018-06-25 11:22 ` [PATCH v2 2/6] coresight: Add helper device type Suzuki K Poulose
2018-06-25 11:22 ` [PATCH v2 3/6] coresight: Introduce support for Coresight Address Translation Unit Suzuki K Poulose
2018-06-25 16:23 ` Joe Perches
2018-06-26 15:59 ` Mathieu Poirier
2018-06-26 17:19 ` Joe Perches
2018-06-25 11:22 ` Suzuki K Poulose [this message]
2018-06-25 20:46 ` [PATCH v2 4/6] dts: bindings: Document device tree binding for CATU Rob Herring
2018-06-25 11:22 ` [PATCH v2 5/6] coresight: catu: Add support for scatter gather tables Suzuki K Poulose
2018-06-25 11:22 ` [PATCH v2 6/6] coresight: catu: Plug in CATU as a backend for ETR buffer Suzuki K Poulose
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