From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
kvmarm@lists.cs.columbia.edu, james.morse@arm.com,
marc.zyngier@arm.com, cdall@kernel.org, eric.auger@redhat.com,
julien.grall@arm.com, will.deacon@arm.com,
catalin.marinas@arm.com, punit.agrawal@arm.com,
qemu-devel@nongnu.org, Suzuki K Poulose <suzuki.poulose@arm.com>
Subject: [PATCH v3 10/20] kvm: arm64: Dynamic configuration of VTTBR mask
Date: Fri, 29 Jun 2018 12:15:30 +0100 [thread overview]
Message-ID: <1530270944-11351-11-git-send-email-suzuki.poulose@arm.com> (raw)
In-Reply-To: <1530270944-11351-1-git-send-email-suzuki.poulose@arm.com>
On arm64 VTTBR_EL2:BADDR holds the base address for the stage2
translation table. The Arm ARM mandates that the bits BADDR[x-1:0]
should be 0, where 'x' is defined for a given IPA Size and the
number of levels for a translation granule size. It is defined
using some magical constants. This patch is a reverse engineered
implementation to calculate the 'x' at runtime for a given ipa and
number of page table levels. See patch for more details.
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Christoffer Dall <cdall@kernel.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
Changes since V2:
- Part 1 of spilt from VTCR & VTTBR dynamic configuration
---
arch/arm64/include/asm/kvm_arm.h | 60 +++++++++++++++++++++++++++++++++++++---
arch/arm64/include/asm/kvm_mmu.h | 25 ++++++++++++++++-
2 files changed, 80 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h
index 3dffd38..c557f45 100644
--- a/arch/arm64/include/asm/kvm_arm.h
+++ b/arch/arm64/include/asm/kvm_arm.h
@@ -140,8 +140,6 @@
* Note that when using 4K pages, we concatenate two first level page tables
* together. With 16K pages, we concatenate 16 first level page tables.
*
- * The magic numbers used for VTTBR_X in this patch can be found in Tables
- * D4-23 and D4-25 in ARM DDI 0487A.b.
*/
#define VTCR_EL2_T0SZ_IPA VTCR_EL2_T0SZ_40B
@@ -175,9 +173,63 @@
#endif
#define VTCR_EL2_FLAGS (VTCR_EL2_COMMON_BITS | VTCR_EL2_TGRAN_FLAGS)
-#define VTTBR_X (VTTBR_X_TGRAN_MAGIC - VTCR_EL2_T0SZ_IPA)
+/*
+ * ARM VMSAv8-64 defines an algorithm for finding the translation table
+ * descriptors in section D4.2.8 in ARM DDI 0487B.b.
+ *
+ * The algorithm defines the expectations on the BaseAddress (for the page
+ * table) bits resolved at each level based on the page size, entry level
+ * and T0SZ. The variable "x" in the algorithm also affects the VTTBR:BADDR
+ * for stage2 page table.
+ *
+ * The value of "x" is calculated as :
+ * x = Magic_N - T0SZ
+ *
+ * where Magic_N is an integer depending on the page size and the entry
+ * level of the page table as below:
+ *
+ * --------------------------------------------
+ * | Entry level | 4K 16K 64K |
+ * --------------------------------------------
+ * | Level: 0 (4 levels) | 28 | - | - |
+ * --------------------------------------------
+ * | Level: 1 (3 levels) | 37 | 31 | 25 |
+ * --------------------------------------------
+ * | Level: 2 (2 levels) | 46 | 42 | 38 |
+ * --------------------------------------------
+ * | Level: 3 (1 level) | - | 53 | 51 |
+ * --------------------------------------------
+ *
+ * We have a magic formula for the Magic_N below.
+ *
+ * Magic_N(PAGE_SIZE, Entry_Level) = 64 - ((PAGE_SHIFT - 3) * Number of levels)
+ *
+ * where number of levels = (4 - Entry_Level).
+ *
+ * So, given that T0SZ = (64 - PA_SHIFT), we can compute 'x' as follows:
+ *
+ * x = (64 - ((PAGE_SHIFT - 3) * Number_of_levels)) - (64 - PA_SHIFT)
+ * = PA_SHIFT - ((PAGE_SHIFT - 3) * Number of levels)
+ *
+ * Here is one way to explain the Magic Formula:
+ *
+ * x = log2(Size_of_Entry_Level_Table)
+ *
+ * Since, we can resolve (PAGE_SHIFT - 3) bits at each level, and another
+ * PAGE_SHIFT bits in the PTE, we have :
+ *
+ * Bits_Entry_level = PA_SHIFT - ((PAGE_SHIFT - 3) * (n - 1) + PAGE_SHIFT)
+ * = PA_SHIFT - (PAGE_SHIFT - 3) * n - 3
+ * where n = number of levels, and since each pointer is 8bytes, we have:
+ *
+ * x = Bits_Entry_Level + 3
+ * = PA_SHIFT - (PAGE_SHIFT - 3) * n
+ *
+ * The only constraint here is that, we have to find the number of page table
+ * levels for a given IPA size (which we do, see stage2_pt_levels())
+ */
+#define ARM64_VTTBR_X(ipa, levels) ((ipa) - ((levels) * (PAGE_SHIFT - 3)))
-#define VTTBR_BADDR_MASK (((UL(1) << (PHYS_MASK_SHIFT - VTTBR_X)) - 1) << VTTBR_X)
#define VTTBR_VMID_SHIFT (UL(48))
#define VTTBR_VMID_MASK(size) (_AT(u64, (1 << size) - 1) << VTTBR_VMID_SHIFT)
diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_mmu.h
index a351722..813a72a 100644
--- a/arch/arm64/include/asm/kvm_mmu.h
+++ b/arch/arm64/include/asm/kvm_mmu.h
@@ -146,7 +146,6 @@ static inline unsigned long __kern_hyp_va(unsigned long v)
#define kvm_phys_shift(kvm) KVM_PHYS_SHIFT
#define kvm_phys_size(kvm) (_AC(1, ULL) << kvm_phys_shift(kvm))
#define kvm_phys_mask(kvm) (kvm_phys_size(kvm) - _AC(1, ULL))
-#define kvm_vttbr_baddr_mask(kvm) VTTBR_BADDR_MASK
static inline bool kvm_page_empty(void *ptr)
{
@@ -503,6 +502,30 @@ static inline int hyp_map_aux_data(void)
#define kvm_phys_to_vttbr(addr) phys_to_ttbr(addr)
+/*
+ * Get the magic number 'x' for VTTBR:BADDR of this KVM instance.
+ * With v8.2 LVA extensions, 'x' should be a minimum of 6 with
+ * 52bit IPS.
+ */
+static inline int arm64_vttbr_x(u32 ipa_shift, u32 levels)
+{
+ int x = ARM64_VTTBR_X(ipa_shift, levels);
+
+ return (IS_ENABLED(CONFIG_ARM64_PA_BITS_52) && x < 6) ? 6 : x;
+}
+
+static inline u64 vttbr_baddr_mask(u32 ipa_shift, u32 levels)
+{
+ unsigned int x = arm64_vttbr_x(ipa_shift, levels);
+
+ return GENMASK_ULL(PHYS_MASK_SHIFT - 1, x);
+}
+
+static inline u64 kvm_vttbr_baddr_mask(struct kvm *kvm)
+{
+ return vttbr_baddr_mask(kvm_phys_shift(kvm), kvm_stage2_levels(kvm));
+}
+
static inline void *stage2_alloc_pgd(struct kvm *kvm)
{
return alloc_pages_exact(stage2_pgd_size(kvm),
--
2.7.4
next prev parent reply other threads:[~2018-06-29 11:16 UTC|newest]
Thread overview: 88+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-29 11:15 [PATCH v3 00/20] arm64: Dynamic & 52bit IPA support Suzuki K Poulose
2018-06-29 11:15 ` [PATCH v3 01/20] virtio: mmio-v1: Validate queue PFN Suzuki K Poulose
2018-06-29 17:42 ` Michael S. Tsirkin
2018-07-03 8:04 ` Suzuki K Poulose
2018-07-04 5:37 ` Michael S. Tsirkin
2018-06-29 11:15 ` [PATCH v3 02/20] virtio: pci-legacy: Validate queue pfn Suzuki K Poulose
2018-06-29 17:42 ` Michael S. Tsirkin
2018-06-29 11:15 ` [PATCH v3 03/20] arm64: Add a helper for PARange to physical shift conversion Suzuki K Poulose
2018-06-29 14:50 ` Auger Eric
2018-06-29 11:15 ` [PATCH v3 04/20] kvm: arm64: Clean up VTCR_EL2 initialisation Suzuki K Poulose
2018-06-29 14:50 ` Auger Eric
2018-06-29 11:15 ` [PATCH v3 05/20] kvm: arm/arm64: Fix stage2_flush_memslot for 4 level page table Suzuki K Poulose
2018-06-29 14:50 ` Auger Eric
2018-07-02 9:59 ` Marc Zyngier
2018-06-29 11:15 ` [PATCH v3 06/20] kvm: arm/arm64: Remove spurious WARN_ON Suzuki K Poulose
2018-06-29 14:51 ` Auger Eric
2018-07-02 10:01 ` Marc Zyngier
2018-06-29 11:15 ` [PATCH v3 07/20] kvm: arm/arm64: Prepare for VM specific stage2 translations Suzuki K Poulose
2018-07-02 10:12 ` Marc Zyngier
2018-07-02 10:25 ` Suzuki K Poulose
2018-07-02 10:51 ` Auger Eric
2018-07-02 10:59 ` Suzuki K Poulose
2018-06-29 11:15 ` [PATCH v3 08/20] kvm: arm/arm64: Abstract stage2 pgd table allocation Suzuki K Poulose
2018-07-02 15:01 ` Auger Eric
2018-06-29 11:15 ` [PATCH v3 09/20] kvm: arm64: Make stage2 page table layout dynamic Suzuki K Poulose
2018-07-02 10:57 ` Suzuki K Poulose
2018-07-02 12:14 ` Auger Eric
2018-07-02 13:24 ` Suzuki K Poulose
2018-07-02 14:46 ` [Qemu-devel] " Auger Eric
2018-06-29 11:15 ` Suzuki K Poulose [this message]
2018-07-02 14:41 ` [PATCH v3 10/20] kvm: arm64: Dynamic configuration of VTTBR mask Auger Eric
2018-07-03 11:54 ` Suzuki K Poulose
2018-07-04 8:24 ` Auger Eric
2018-07-04 8:29 ` Suzuki K Poulose
2018-06-29 11:15 ` [PATCH v3 11/20] kvm: arm64: Helper for computing VTCR_EL2.SL0 Suzuki K Poulose
2018-07-02 14:59 ` Auger Eric
2018-06-29 11:15 ` [PATCH v3 12/20] kvm: arm64: Add helper for loading the stage2 setting for a VM Suzuki K Poulose
2018-07-02 19:13 ` Auger Eric
2018-06-29 11:15 ` [PATCH v3 13/20] kvm: arm64: Configure VTCR per VM Suzuki K Poulose
2018-07-02 12:16 ` Marc Zyngier
2018-07-03 10:48 ` Suzuki K Poulose
2018-07-03 10:58 ` Marc Zyngier
2018-06-29 11:15 ` [PATCH v3 14/20] kvm: arm/arm64: Expose supported physical address limit for VM Suzuki K Poulose
2018-06-29 11:15 ` [PATCH v3 15/20] kvm: arm/arm64: Allow tuning the physical address size " Suzuki K Poulose
2018-07-02 13:13 ` Marc Zyngier
2018-07-02 13:31 ` Suzuki K Poulose
2018-07-04 15:51 ` Will Deacon
2018-07-04 22:03 ` Suzuki K Poulose
2018-07-06 13:49 ` Suzuki K Poulose
2018-07-06 15:09 ` Marc Zyngier
2018-07-06 16:39 ` Suzuki K Poulose
2018-07-09 11:23 ` Dave Martin
2018-07-09 12:29 ` Marc Zyngier
2018-07-09 13:37 ` Dave Martin
2018-07-10 16:38 ` Suzuki K Poulose
2018-07-10 17:03 ` Dave Martin
2018-07-11 9:05 ` Suzuki K Poulose
2018-07-11 10:38 ` Dave Martin
2018-06-29 11:15 ` [PATCH v3 16/20] kvm: arm64: Switch to per VM IPA limit Suzuki K Poulose
2018-07-02 13:32 ` Marc Zyngier
2018-07-02 13:53 ` Suzuki K Poulose
2018-06-29 11:15 ` [PATCH v3 17/20] vgic: Add support for 52bit guest physical address Suzuki K Poulose
2018-07-04 8:09 ` Auger Eric
2018-06-29 11:15 ` [PATCH v3 18/20] kvm: arm64: Add support for handling 52bit IPA Suzuki K Poulose
2018-07-02 13:43 ` Marc Zyngier
2018-06-29 11:15 ` [PATCH v3 19/20] kvm: arm64: Allow IPA size supported by the system Suzuki K Poulose
2018-07-02 13:50 ` Marc Zyngier
2018-07-02 13:54 ` Suzuki K Poulose
2018-06-29 11:15 ` [PATCH v3 20/20] kvm: arm64: Fall back to normal stage2 entry level Suzuki K Poulose
2018-06-29 11:15 ` [kvmtool test PATCH 21/24] kvmtool: Allow backends to run checks on the KVM device fd Suzuki K Poulose
2018-06-29 11:15 ` [kvmtool test PATCH 22/24] kvmtool: arm64: Add support for guest physical address size Suzuki K Poulose
2018-07-04 14:09 ` Will Deacon
2018-07-04 15:00 ` Julien Grall
2018-07-04 15:52 ` Will Deacon
2018-07-05 12:47 ` Julien Grall
2018-07-05 13:20 ` Marc Zyngier
2018-07-05 13:46 ` Auger Eric
2018-07-05 14:12 ` Suzuki K Poulose
2018-07-05 14:15 ` Marc Zyngier
2018-07-05 14:37 ` Auger Eric
2018-06-29 11:15 ` [kvmtool test PATCH 23/24] kvmtool: arm64: Switch memory layout Suzuki K Poulose
2018-06-29 11:15 ` [kvmtool test PATCH 24/24] kvmtool: arm: Add support for creating VM with PA size Suzuki K Poulose
2018-07-04 14:22 ` Will Deacon
2018-07-04 14:41 ` Marc Zyngier
2018-07-04 15:51 ` Will Deacon
2018-07-05 7:51 ` Peter Maydell
2018-07-05 7:58 ` Auger Eric
2018-07-04 15:58 ` Suzuki K Poulose
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