From: Fenghua Yu <fenghua.yu@intel.com>
To: "Thomas Gleixner" <tglx@linutronix.de>,
"Ingo Molnar" <mingo@redhat.com>, "H Peter Anvin" <hpa@zytor.com>
Cc: "Ashok Raj" <ashok.raj@intel.com>,
"Alan Cox" <alan@linux.intel.com>,
"Dave Hansen" <dave.hansen@intel.com>,
"Peter Zijlstra" <peterz@infradead.org>,
"Rafael Wysocki" <rafael.j.wysocki@intel.com>,
"Tony Luck" <tony.luck@intel.com>,
"Ravi V Shankar" <ravi.v.shankar@intel.com>,
"linux-kernel" <linux-kernel@vger.kernel.org>,
"x86" <x86@kernel.org>, Fenghua Yu <fenghua.yu@intel.com>
Subject: [PATCH v2 2/4] x86/split_lock: Align x86_capability to unsigned long to avoid split locked access
Date: Fri, 29 Jun 2018 07:33:25 -0700 [thread overview]
Message-ID: <1530282807-66555-3-git-send-email-fenghua.yu@intel.com> (raw)
In-Reply-To: <1530282807-66555-1-git-send-email-fenghua.yu@intel.com>
set_cpu_cap() calls locked BTS and clear_cpu_cap() calls locked BTR to
operate on bitmap defined in x86_capability.
Locked BTS/BTR accesses a single unsigned long location. In 64-bit mode,
the location is at:
base address of x86_capability + (bit offset in x86_capability % 64) * 8
Since base address of x86_capability may not aligned to unsigned long,
the single unsigned long location may cross two cache lines and
accessing the location by locked BTS/BTR intructions will trigger #AC.
To fix the split lock issue, align x86_capability to unsigned long so that
the location will be always within one cache line.
Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
---
arch/x86/include/asm/processor.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index cfd29ee8c3da..5ad6ba4657a2 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -105,7 +105,8 @@ struct cpuinfo_x86 {
__u32 extended_cpuid_level;
/* Maximum supported CPUID level, -1=no CPUID: */
int cpuid_level;
- __u32 x86_capability[NCAPINTS + NBUGINTS];
+ __u32 x86_capability[NCAPINTS + NBUGINTS]
+ __aligned(sizeof(unsigned long));
char x86_vendor_id[16];
char x86_model_id[64];
/* in KB - valid for CPUS which support this call: */
--
2.5.0
next prev parent reply other threads:[~2018-06-29 14:35 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-29 14:33 [PATCH v2 0/4] x86/split_lock: Enable #AC exception for split locked accesses Fenghua Yu
2018-06-29 14:33 ` [PATCH v2 1/4] x86/split_lock: Enumerate #AC exception for split locked access feature Fenghua Yu
2018-06-29 14:56 ` Dave Hansen
2018-06-29 16:23 ` Thomas Gleixner
2018-06-29 16:32 ` Dave Hansen
2018-07-04 20:07 ` Eduardo Habkost
2018-07-10 18:45 ` Fenghua Yu
2018-07-10 18:54 ` Dave Hansen
2018-07-10 19:47 ` Thomas Gleixner
2018-07-11 19:59 ` Dave Hansen
2018-07-12 20:00 ` Thomas Gleixner
2018-06-29 14:33 ` Fenghua Yu [this message]
2018-06-29 16:04 ` [PATCH v2 2/4] x86/split_lock: Align x86_capability to unsigned long to avoid split locked access Dave Hansen
2018-06-29 16:35 ` Thomas Gleixner
2018-06-29 19:03 ` Fenghua Yu
2018-06-29 20:08 ` Thomas Gleixner
2018-06-29 20:38 ` Fenghua Yu
2018-06-29 20:48 ` Dave Hansen
2018-06-29 21:10 ` Fenghua Yu
2018-06-29 21:44 ` Thomas Gleixner
2018-06-30 0:00 ` Fenghua Yu
2018-06-30 0:14 ` Fenghua Yu
2018-06-30 6:23 ` Thomas Gleixner
2018-07-02 12:18 ` Peter Zijlstra
2018-07-02 14:11 ` Fenghua Yu
2018-06-29 14:33 ` [PATCH v2 3/4] x86/split_lock: Handle #AC exception for split lock Fenghua Yu
2018-06-29 16:29 ` Dave Hansen
2018-06-29 16:33 ` Luck, Tony
2018-06-29 17:16 ` Fenghua Yu
2018-06-29 17:29 ` Dave Hansen
2018-06-29 17:39 ` Fenghua Yu
2018-06-29 17:47 ` Dave Hansen
2018-06-29 14:33 ` [PATCH v2 4/4] x86/split_lock: Disable #AC for split locked accesses Fenghua Yu
2018-06-29 16:31 ` Dave Hansen
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