From: Ben Dooks <ben.dooks@codethink.co.uk>
To: linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org
Cc: pdeschrijver@nvidia.com, pgaikwad@nvidia.com,
jonathanh@nvidia.co, thierry.reding@gmail.com,
linux-kernel@lists.codethink.co.uk,
Ben Dooks <ben.dooks@codethink.co.uk>
Subject: [PATCH 2/8] clk: tegra: host1x has fractional divider
Date: Fri, 20 Jul 2018 14:45:26 +0100 [thread overview]
Message-ID: <20180720134532.13148-3-ben.dooks@codethink.co.uk> (raw)
In-Reply-To: <20180720134532.13148-1-ben.dooks@codethink.co.uk>
The host1x clock according to both tegra2 and tegra3 manuals is
an 8bit divider with lsb being fractional. This is running into
an issue where the host1x is being set on a tegra20a system to
266.4MHz but ends up at 222MHz instead.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
---
drivers/clk/tegra/clk-tegra-periph.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c
index 2acba2986bc6..8fa1cecf18a0 100644
--- a/drivers/clk/tegra/clk-tegra-periph.c
+++ b/drivers/clk/tegra/clk-tegra-periph.c
@@ -644,7 +644,7 @@ static struct tegra_periph_init_data periph_clks[] = {
INT("vde", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VDE, 61, 0, tegra_clk_vde),
INT("vi", mux_pllm_pllc_pllp_plla, CLK_SOURCE_VI, 20, 0, tegra_clk_vi),
INT("epp", mux_pllm_pllc_pllp_plla, CLK_SOURCE_EPP, 19, 0, tegra_clk_epp),
- INT("host1x", mux_pllm_pllc_pllp_plla, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x),
+ MUX("host1x", mux_pllm_pllc_pllp_plla, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x),
INT("mpe", mux_pllm_pllc_pllp_plla, CLK_SOURCE_MPE, 60, 0, tegra_clk_mpe),
INT("2d", mux_pllm_pllc_pllp_plla, CLK_SOURCE_2D, 21, 0, tegra_clk_gr2d),
INT("3d", mux_pllm_pllc_pllp_plla, CLK_SOURCE_3D, 24, 0, tegra_clk_gr3d),
--
2.18.0
next prev parent reply other threads:[~2018-07-20 13:45 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-20 13:45 tegra clock updates and fixes Ben Dooks
2018-07-20 13:45 ` [PATCH 1/8] clk: tegra: implement reset status callback Ben Dooks
2018-07-20 13:45 ` Ben Dooks [this message]
2018-07-23 8:50 ` [PATCH 2/8] clk: tegra: host1x has fractional divider Peter De Schrijver
2018-07-23 9:32 ` Ben Dooks
2018-07-23 11:12 ` Peter De Schrijver
2018-07-23 11:32 ` Ben Dooks
2018-07-20 13:45 ` [PATCH 3/8] clk: tegra: fix fractional clocks for VDI, VI, EPP, MPE, 2D and 3D Ben Dooks
2018-07-23 8:50 ` Peter De Schrijver
2018-07-20 13:45 ` [PATCH 4/8] clk: tegra: fix MUX_I2S_SPDIF macro Ben Dooks
2018-07-20 13:45 ` [PATCH 5/8] clk: tegra: add mux-only clock option Ben Dooks
2018-07-20 13:45 ` [PATCH 6/8] clk: tegra30: add 2d and 3d idle clocks Ben Dooks
2018-07-22 11:55 ` Dmitry Osipenko
2018-07-23 8:28 ` Ben Dooks
2018-07-23 11:33 ` Dmitry Osipenko
2018-07-23 11:37 ` Ben Dooks
2018-07-23 13:05 ` Dmitry Osipenko
2018-07-24 11:31 ` Dmitry Osipenko
2018-07-24 12:32 ` Ben Dooks
2018-07-20 13:45 ` [PATCH 7/8] clk: tegra: replace warn on with single line Ben Dooks
2018-07-20 13:45 ` [PATCH 8/8] clk: tegra: show clock name in error from _calc_rate Ben Dooks
2018-07-26 13:32 ` [Linux-kernel] tegra clock updates and fixes Ben Dooks
2018-07-26 15:22 ` Stephen Boyd
2018-07-27 8:22 ` Ben Dooks
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