From: Icenowy Zheng <icenowy@aosc.io>
To: Rob Herring <robh+dt@kernel.org>,
Maxime Ripard <maxime.ripard@bootlin.com>,
Chen-Yu Tsai <wens@csie.org>,
Kishon Vijay Abraham I <kishon@ti.com>
Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com,
Icenowy Zheng <icenowy@aosc.io>
Subject: [PATCH v3 8/9] arm64: allwinner: dts: h6: add USB3 device nodes
Date: Sun, 22 Jul 2018 13:57:38 +0800 [thread overview]
Message-ID: <20180722055739.26464-9-icenowy@aosc.io> (raw)
In-Reply-To: <20180722055739.26464-1-icenowy@aosc.io>
Allwinner H6 SoC features USB3 functionality, with a DWC3 controller and
a custom PHY.
Add device tree nodes for them.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
---
Changes in v3:
- Changed the dwc3 clock according to the user manual.
- Added Chen-Yu's Review tag.
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 32 ++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 454844e8b063..59c448726a10 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -290,6 +290,38 @@
status = "disabled";
};
+ dwc3: dwc3@5200000 {
+ compatible = "snps,dwc3";
+ reg = <0x05200000 0x10000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_XHCI>,
+ <&ccu CLK_BUS_XHCI>,
+ <&osc32k>;
+ clock-names = "ref", "bus_early", "suspend";
+ resets = <&ccu RST_BUS_XHCI>;
+ /*
+ * The datasheet of the chip doesn't declare the
+ * peripheral function, and there's no boards known
+ * to have a USB Type-B port routed to the port.
+ * In addition, no one has tested the peripheral
+ * function yet.
+ * So set the dr_mode to "host" in the DTSI file.
+ */
+ dr_mode = "host";
+ phys = <&usb3phy>;
+ phy-names = "usb3-phy";
+ status = "disabled";
+ };
+
+ usb3phy: phy@5210000 {
+ compatible = "allwinner,sun50i-h6-usb3-phy";
+ reg = <0x5210000 0x10000>;
+ clocks = <&ccu CLK_USB_PHY1>;
+ resets = <&ccu RST_USB_PHY1>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
ehci3: usb@5311000 {
compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
reg = <0x05311000 0x100>;
--
2.18.0
next prev parent reply other threads:[~2018-07-22 6:01 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-22 5:57 [PATCH v3 0/9] Allwinner H6 USB support Icenowy Zheng
2018-07-22 5:57 ` [PATCH v3 1/9] phy: sun4i-usb: add support for missing USB PHY index Icenowy Zheng
2018-07-22 5:57 ` [PATCH v3 2/9] phy: sun4i-usb: add support for H6 USB2 PHY Icenowy Zheng
2018-07-22 5:57 ` [PATCH v3 3/9] arm64: allwinner: dts: h6: add USB2-related device nodes Icenowy Zheng
2018-07-22 5:57 ` [PATCH v3 4/9] arm64: allwinner: dts: h6: add USB Vbus regulator Icenowy Zheng
2018-07-22 5:57 ` [PATCH v3 5/9] arm64: allwinner: dts: h6: enable USB2 on Pine H64 Icenowy Zheng
2018-07-22 5:57 ` [PATCH v3 6/9] dt-bindings: phy: add binding for Allwinner USB3 PHY Icenowy Zheng
2018-07-22 6:10 ` [linux-sunxi] " Chen-Yu Tsai
2018-07-25 15:31 ` Rob Herring
2018-07-25 15:38 ` Icenowy Zheng
2018-07-22 5:57 ` [PATCH v3 7/9] phy: allwinner: add phy driver for USB3 PHY on Allwinner H6 SoC Icenowy Zheng
2018-07-22 5:57 ` Icenowy Zheng [this message]
2018-07-22 5:57 ` [PATCH v3 9/9] arm64: allwinner: dts: h6: enable USB3 port on Pine H64 Icenowy Zheng
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