From: Wei Wang <wei.w.wang@intel.com>
To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
pbonzini@redhat.com, ak@linux.intel.com
Cc: kan.liang@intel.com, peterz@infradead.org, mingo@redhat.com,
rkrcmar@redhat.com, like.xu@intel.com, wei.w.wang@intel.com
Subject: [PATCH v2 4/8] KVM/x86: expose MSR_IA32_PERF_CAPABILITIES to the guest
Date: Thu, 6 Sep 2018 19:30:52 +0800 [thread overview]
Message-ID: <1536233456-12173-5-git-send-email-wei.w.wang@intel.com> (raw)
In-Reply-To: <1536233456-12173-1-git-send-email-wei.w.wang@intel.com>
Bits [0, 5] of MSR_IA32_PERF_CAPABILITIES tell about the format of
the addresses stored in the LBR stack. Expose those bits to the guest
when the guest lbr feature is enabled.
Signed-off-by: Like Xu <like.xu@intel.com>
Signed-off-by: Wei Wang <wei.w.wang@intel.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Andi Kleen <ak@linux.intel.com>
---
arch/x86/include/asm/perf_event.h | 2 ++
arch/x86/kvm/cpuid.c | 2 +-
arch/x86/kvm/vmx.c | 7 +++++++
3 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index f40e80a..161165f 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -79,6 +79,8 @@
#define ARCH_PERFMON_BRANCH_MISSES_RETIRED 6
#define ARCH_PERFMON_EVENTS_COUNT 7
+#define PERF_CAP_MASK_LBR_FMT 0x3f
+
/*
* Intel "Architectural Performance Monitoring" CPUID
* detection/enumeration details:
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 7bcfa61..3b8a57b 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -365,7 +365,7 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
0 /* DS-CPL, VMX, SMX, EST */ |
0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
- F(FMA) | F(CX16) | 0 /* xTPR Update, PDCM */ |
+ F(FMA) | F(CX16) | 0 /* xTPR Update*/ | F(PDCM) |
F(PCID) | 0 /* Reserved, DCA */ | F(XMM4_1) |
F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index 7a62c1c..d5eba8e 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -4134,6 +4134,13 @@ static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
!guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
return 1;
/* Otherwise falls through */
+ case MSR_IA32_PERF_CAPABILITIES:
+ if (!boot_cpu_has(X86_FEATURE_PDCM))
+ return 1;
+ msr_info->data = native_read_msr(MSR_IA32_PERF_CAPABILITIES);
+ if (vcpu->kvm->arch.guest_lbr)
+ msr_info->data &= PERF_CAP_MASK_LBR_FMT;
+ break;
default:
msr = find_msr_entry(vmx, msr_info->index);
if (msr) {
--
2.7.4
next prev parent reply other threads:[~2018-09-06 12:01 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-06 11:30 [PATCH v2 0/8] Guest LBR Enabling Wei Wang
2018-09-06 11:30 ` [PATCH v2 1/8] perf/x86: add a function to get the lbr stack Wei Wang
2018-09-07 3:28 ` Andi Kleen
2018-09-07 6:45 ` Wei Wang
2018-09-06 11:30 ` [PATCH v2 2/8] KVM/x86: KVM_CAP_X86_GUEST_LBR Wei Wang
2018-09-06 11:30 ` [PATCH v2 3/8] KVM/vmx: Pass through the lbr stack to a guest Wei Wang
2018-09-06 11:30 ` Wei Wang [this message]
2018-09-06 11:30 ` [PATCH v2 5/8] KVM/x86: enable the guest to access the debugctl msr Wei Wang
2018-09-06 11:30 ` [PATCH v2 6/8] perf/x86/intel/lbr: guest requesting KVM for lbr stack save/restore Wei Wang
2018-09-07 3:27 ` Andi Kleen
2018-09-07 5:24 ` Wei Wang
2018-09-07 14:10 ` Andi Kleen
2018-09-07 15:20 ` Wang, Wei W
2018-09-07 20:05 ` Andi Kleen
2018-09-08 1:34 ` Wang, Wei W
2018-09-06 11:30 ` [PATCH v2 7/8] KVM: PMU: support to save/restore the guest lbr stack on vCPU switching Wei Wang
2018-09-07 14:36 ` Jann Horn
2018-09-07 15:21 ` Wang, Wei W
2018-09-18 0:58 ` Gonglei (Arei)
2018-09-18 2:56 ` Andi Kleen
2018-09-18 9:57 ` Wei Wang
2018-09-18 10:34 ` Gonglei (Arei)
2018-09-06 11:30 ` [PATCH v2 8/8] perf/x86/intel/lbr: add the guest_lbr boolean to cpuc Wei Wang
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