From: Anson Huang <Anson.Huang@nxp.com>
To: shawnguo@kernel.org, s.hauer@pengutronix.de,
kernel@pengutronix.de, fabio.estevam@nxp.com, robh+dt@kernel.org,
mark.rutland@arm.com, rjw@rjwysocki.net, viresh.kumar@linaro.org,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org
Cc: Linux-imx@nxp.com
Subject: [PATCH V2 1/2] ARM: dts: imx6ul: use nvmem-cells for cpu speed grading
Date: Mon, 17 Sep 2018 11:17:43 +0800 [thread overview]
Message-ID: <1537154264-23252-1-git-send-email-Anson.Huang@nxp.com> (raw)
On i.MX6UL, accessing OCOTP directly is wrong because the ocotp clock
needs to be enabled first, so use the nvmem-cells binding instead.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
no change since V1.
arch/arm/boot/dts/imx6ul.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index 5ef4320..ff8c6de 100644
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -89,6 +89,8 @@
"pll1_sys";
arm-supply = <®_arm>;
soc-supply = <®_soc>;
+ nvmem-cells = <&cpu_speed_grade>;
+ nvmem-cell-names = "speed_grade";
};
};
@@ -943,6 +945,10 @@
tempmon_temp_grade: temp-grade@20 {
reg = <0x20 4>;
};
+
+ cpu_speed_grade: speed-grade@10 {
+ reg = <0x10 4>;
+ };
};
lcdif: lcdif@21c8000 {
--
2.7.4
next reply other threads:[~2018-09-17 3:23 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-17 3:17 Anson Huang [this message]
2018-09-17 3:17 ` [PATCH V2 2/2] cpufreq: imx6q: read OCOTP through nvmem for imx6ul/imx6ull Anson Huang
2018-10-01 5:57 ` Viresh Kumar
2018-10-08 1:07 ` Anson Huang
2018-09-26 9:20 ` [PATCH V2 1/2] ARM: dts: imx6ul: use nvmem-cells for cpu speed grading Shawn Guo
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