From: Kishon Vijay Abraham I <kishon@ti.com>
To: Bjorn Helgaas <bhelgaas@google.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Murali Karicheri <m-karicheri2@ti.com>,
Jingoo Han <jingoohan1@gmail.com>,
Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Cc: Rob Herring <robh+dt@kernel.org>, <linux-pci@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
Kishon Vijay Abraham I <kishon@ti.com>
Subject: [PATCH 14/19] PCI: keystone: Get number of OB windows from DT and cleanup MEM space configuration
Date: Mon, 15 Oct 2018 18:37:16 +0530 [thread overview]
Message-ID: <20181015130721.5535-15-kishon@ti.com> (raw)
In-Reply-To: <20181015130721.5535-1-kishon@ti.com>
Instead of having a fixed outbound window count, get the number of
outbound windows from device tree. Also cleanup memory space configuration
here by adding macros for constants.
While at that also use BIT() macro for OB_XLAT_EN_VAL.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/pci/controller/dwc/pci-keystone.c | 47 +++++++++++++++--------
1 file changed, 31 insertions(+), 16 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c
index adf98dc0035c..68b080aef3ac 100644
--- a/drivers/pci/controller/dwc/pci-keystone.c
+++ b/drivers/pci/controller/dwc/pci-keystone.c
@@ -41,7 +41,7 @@
#define LTSSM_STATE_MASK 0x1f
#define LTSSM_STATE_L0 0x11
#define DBI_CS2_EN_VAL 0x20
-#define OB_XLAT_EN_VAL 2
+#define OB_XLAT_EN_VAL BIT(1)
/* Application registers */
#define CMD_STATUS 0x004
@@ -53,11 +53,10 @@
#define CFG_TYPE1 BIT(24)
#define OB_SIZE 0x030
-#define CFG_PCIM_WIN_SZ_IDX 3
-#define CFG_PCIM_WIN_CNT 32
#define SPACE0_REMOTE_CFG_OFFSET 0x1000
#define OB_OFFSET_INDEX(n) (0x200 + (8 * (n)))
#define OB_OFFSET_HI(n) (0x204 + (8 * (n)))
+#define OB_WIN_SIZE 8 /* 8MB */
/* IRQ register defines */
#define IRQ_EOI 0x050
@@ -87,6 +86,11 @@
#define ERR_IRQ_ENABLE_SET 0x1c8
#define ERR_IRQ_ENABLE_CLR 0x1cc
+#define OB_OFFSET_INDEX(n) (0x200 + (8 * (n)))
+#define OB_ENABLEN BIT(0)
+
+#define OB_OFFSET_HI(n) (0x204 + (8 * (n)))
+
/* Config space registers */
#define DEBUG0 0x728
@@ -111,6 +115,7 @@ struct keystone_pcie {
int num_msi_host_irqs;
int msi_host_irqs[MAX_MSI_HOST_IRQS];
int num_lanes;
+ u32 num_viewport;
struct phy **phy;
struct device_link **link;
struct device_node *msi_intc_np;
@@ -341,11 +346,13 @@ static void ks_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie)
static void ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
{
+ u32 val;
+ u32 num_viewport = ks_pcie->num_viewport;
struct dw_pcie *pci = ks_pcie->pci;
struct pcie_port *pp = &pci->pp;
- u32 start = pp->mem->start, end = pp->mem->end;
- int i, tr_size;
- u32 val;
+ u64 start = pp->mem->start;
+ u64 end = pp->mem->end;
+ int i;
/* Disable BARs for inbound access */
ks_pcie_set_dbi_mode(ks_pcie);
@@ -353,21 +360,21 @@ static void ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0);
ks_pcie_clear_dbi_mode(ks_pcie);
- /* Set outbound translation size per window division */
- ks_pcie_app_writel(ks_pcie, OB_SIZE, CFG_PCIM_WIN_SZ_IDX & 0x7);
-
- tr_size = (1 << (CFG_PCIM_WIN_SZ_IDX & 0x7)) * SZ_1M;
+ val = ilog2(OB_WIN_SIZE);
+ ks_pcie_app_writel(ks_pcie, OB_SIZE, val);
/* Using Direct 1:1 mapping of RC <-> PCI memory space */
- for (i = 0; (i < CFG_PCIM_WIN_CNT) && (start < end); i++) {
- ks_pcie_app_writel(ks_pcie, OB_OFFSET_INDEX(i), start | 1);
- ks_pcie_app_writel(ks_pcie, OB_OFFSET_HI(i), 0);
- start += tr_size;
+ for (i = 0; i < num_viewport && (start < end); i++) {
+ ks_pcie_app_writel(ks_pcie, OB_OFFSET_INDEX(i),
+ lower_32_bits(start) | OB_ENABLEN);
+ ks_pcie_app_writel(ks_pcie, OB_OFFSET_HI(i),
+ upper_32_bits(start));
+ start += OB_WIN_SIZE;
}
- /* Enable OB translation */
val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
- ks_pcie_app_writel(ks_pcie, CMD_STATUS, OB_XLAT_EN_VAL | val);
+ val |= OB_XLAT_EN_VAL;
+ ks_pcie_app_writel(ks_pcie, CMD_STATUS, val);
}
static int ks_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
@@ -902,6 +909,7 @@ static int __init ks_pcie_probe(struct platform_device *pdev)
struct dw_pcie *pci;
struct keystone_pcie *ks_pcie;
struct device_link **link;
+ u32 num_viewport;
struct phy **phy;
u32 num_lanes;
char name[10];
@@ -919,6 +927,12 @@ static int __init ks_pcie_probe(struct platform_device *pdev)
pci->dev = dev;
pci->ops = &ks_pcie_dw_pcie_ops;
+ ret = of_property_read_u32(np, "num-viewport", &num_viewport);
+ if (ret < 0) {
+ dev_err(dev, "unable to read *num-viewport* property\n");
+ return ret;
+ }
+
ret = of_property_read_u32(np, "num-lanes", &num_lanes);
if (ret)
num_lanes = 1;
@@ -953,6 +967,7 @@ static int __init ks_pcie_probe(struct platform_device *pdev)
ks_pcie->pci = pci;
ks_pcie->link = link;
ks_pcie->num_lanes = num_lanes;
+ ks_pcie->num_viewport = num_viewport;
ks_pcie->phy = phy;
ret = ks_pcie_enable_phy(ks_pcie);
--
2.17.1
next prev parent reply other threads:[~2018-10-15 13:09 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-15 13:07 [PATCH 00/19] PCI: Cleanup pci-keystone driver Kishon Vijay Abraham I
2018-10-15 13:07 ` [PATCH 01/19] PCI: keystone: Use quirk to limit MRRS for K2G Kishon Vijay Abraham I
2018-10-15 13:07 ` [PATCH 02/19] PCI: keystone: Use quirk to set MRRS for PCI host bridge Kishon Vijay Abraham I
2018-10-15 13:07 ` [PATCH 03/19] PCI: keystone: Move dw_pcie_setup_rc out of ks_pcie_establish_link() Kishon Vijay Abraham I
2018-10-15 13:07 ` [PATCH 04/19] PCI: keystone: Do not initiate link training multiple times Kishon Vijay Abraham I
2018-10-15 13:07 ` [PATCH 05/19] PCI: keystone: Remove unused argument from ks_dw_pcie_host_init() Kishon Vijay Abraham I
2018-10-15 13:07 ` [PATCH 06/19] PCI: keystone: Merge pci-keystone-dw.c and pci-keystone.c Kishon Vijay Abraham I
2018-10-15 13:07 ` [PATCH 07/19] PCI: keystone: Remove redundant platform_set_drvdata Kishon Vijay Abraham I
2018-10-15 13:07 ` [PATCH 08/19] PCI: keystone: Use uniform function naming convention Kishon Vijay Abraham I
2018-10-15 13:07 ` [PATCH 09/19] dt-bindings: PCI: keystone: Add bindings to get device control module Kishon Vijay Abraham I
2018-10-15 13:07 ` [PATCH 10/19] PCI: keystone: Use syscon APIs to get device id from " Kishon Vijay Abraham I
2018-10-15 13:07 ` [PATCH 11/19] PCI: keystone: Cleanup PHY handling Kishon Vijay Abraham I
2018-10-16 17:06 ` Lorenzo Pieralisi
2018-10-17 3:21 ` Kishon Vijay Abraham I
2018-10-15 13:07 ` [PATCH 12/19] PCI: keystone: Invoke pm_runtime APIs to enable clock Kishon Vijay Abraham I
2018-10-15 13:07 ` [PATCH 13/19] PCI: keystone: Cleanup configuration space access Kishon Vijay Abraham I
2018-10-15 13:07 ` Kishon Vijay Abraham I [this message]
2018-10-15 13:07 ` [PATCH 15/19] PCI: keystone: Cleanup set_dbi_mode and get_dbi_mode Kishon Vijay Abraham I
2018-10-15 13:07 ` [PATCH 16/19] PCI: keystone: Cleanup ks_pcie_link_up() Kishon Vijay Abraham I
2018-10-15 13:07 ` [PATCH 17/19] PCI: keystone: Add debug error message for all errors Kishon Vijay Abraham I
2018-10-15 13:07 ` [PATCH 18/19] PCI: keystone: Reorder header file in alphabetical order Kishon Vijay Abraham I
2018-10-15 13:07 ` [PATCH 19/19] PCI: keystone: Cleanup macros defined in pci-keystone.c Kishon Vijay Abraham I
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20181015130721.5535-15-kishon@ti.com \
--to=kishon@ti.com \
--cc=bhelgaas@google.com \
--cc=devicetree@vger.kernel.org \
--cc=gustavo.pimentel@synopsys.com \
--cc=jingoohan1@gmail.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=lorenzo.pieralisi@arm.com \
--cc=m-karicheri2@ti.com \
--cc=robh+dt@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).