From patchwork Sun Jan 17 10:07:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 1366445 Return-Path: Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CEE37C433DB for ; Sun, 17 Jan 2021 10:09:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A25262065D for ; Sun, 17 Jan 2021 10:09:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728421AbhAQKI4 (ORCPT ); Sun, 17 Jan 2021 05:08:56 -0500 Received: from mail.kernel.org ([198.145.29.99]:43716 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727967AbhAQKIB (ORCPT ); Sun, 17 Jan 2021 05:08:01 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id 94D58206E5; Sun, 17 Jan 2021 10:07:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1610878041; bh=3MHx5UbB1ooomqCTWXY1+5z312KLXluxdGw1tLFu/Co=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lhFoXgQNun3F2vQZY4i8wjtUurHO6HcVwDGozy5RewI86FyrzFBbMxDnMjWfw5qQd fcfkK87eLWOMheQLQSnR29X//wc3OeV3stfipq3vQcX2Y4GZh7gr13xQxRwgKru6IJ 8XGT+lnlvBRZ3MarYDN6x8/MFk+g9d5Zt38Ow1Lo3gdNsMh9cYs3OILrS0xRE/GMqM xfTVxB7JezXouDzPiNG8MdX17WSs+xNhKEL/+Dn/m1YVeIezRzDdkB0nOh09HC7quI gOwnr9G3E/zJ59kwcUaQQ/5ekXMPO3m6b/b/467g8wfBPHSOpIiAlYi7ViI44E82D2 QgvyOMyPv2YNQ== Received: by wens.tw (Postfix, from userid 1000) id AD6075F839; Sun, 17 Jan 2021 18:07:17 +0800 (CST) From: Chen-Yu Tsai To: Rob Herring , Heiko Stuebner Cc: Chen-Yu Tsai , linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 1/3] arm64: dts: rockchip: rk3328: Add clock_in_out property to gmac2phy node Date: Sun, 17 Jan 2021 18:07:08 +0800 Message-Id: <20210117100710.4857-2-wens@kernel.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210117100710.4857-1-wens@kernel.org> References: <20210117100710.4857-1-wens@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Chen-Yu Tsai The gmac2phy is integrated with the PHY within the SoC. Any properties related to this integration can be included in the .dtsi file, instead of having board dts files specify them separately. Add the clock_in_out property to specify the direction of the PHY clock. This is the minimum required to have gmac2phy working on Linux. Other examples include assigned-clocks, assigned-clock-rates, and assigned-clock-parents properties, but the hardware default plus the implementation requesting the appropriate clock rate also works. Fixes: 9c4cc910fe28 ("ARM64: dts: rockchip: Add gmac2phy node support for rk3328") Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index db0d5c8e5f96..93c734d8a46c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -928,6 +928,7 @@ gmac2phy: ethernet@ff550000 { phy-mode = "rmii"; phy-handle = <&phy>; snps,txpbl = <0x4>; + clock_in_out = "output"; status = "disabled"; mdio { From patchwork Sun Jan 17 10:07:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 1366443 Return-Path: Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3EA60C433DB for ; Sun, 17 Jan 2021 10:08:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 08ACB2065D for ; Sun, 17 Jan 2021 10:08:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728326AbhAQKIW (ORCPT ); Sun, 17 Jan 2021 05:08:22 -0500 Received: from mail.kernel.org ([198.145.29.99]:43696 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727838AbhAQKIB (ORCPT ); Sun, 17 Jan 2021 05:08:01 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id 975642074F; Sun, 17 Jan 2021 10:07:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1610878040; bh=vTiBApCzqK9dM+81eGRA53o9IWiK4KFj+sBqbGi2ZPE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NiUTGO/iZC6jp/Vz1a47aMaebZzowHkE+6UzVE2t4KF60lyZ6M9kfbrXm7swz54fC EJtJqxLd8/H4rLgQYjmRV9OGNzPex8C2yVGkALwNAVmJ6/Olmue/gnCCC2beAit0nW ovws8rysmfDOTqcLwpoSqbnQH+V6ApL3VIAbqNYY5ibzPI5ETZY59NmY/LkLfhHEUC MzZQ9+D8q7AuWSLhIQwIv7MhJ4X5jEy9DmJTg+MOgLNnLe1obqsPFjlOeY2rKuk6Il 5d7VIta5ox1PtHhfrq6QawQsGHlqmxVhCHqVToyg/g2FQ/HfqaC4t0vA7IT39Zqieb 8zowSHo0nG0Kw== Received: by wens.tw (Postfix, from userid 1000) id BA4445FB90; Sun, 17 Jan 2021 18:07:17 +0800 (CST) From: Chen-Yu Tsai To: Rob Herring , Heiko Stuebner Cc: Chen-Yu Tsai , linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 2/3] dt-bindings: arm: rockchip: Add Radxa ROCK Pi E Date: Sun, 17 Jan 2021 18:07:09 +0800 Message-Id: <20210117100710.4857-3-wens@kernel.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210117100710.4857-1-wens@kernel.org> References: <20210117100710.4857-1-wens@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Chen-Yu Tsai Radxa ROCK Pi E is a router oriented SBC based on Rockchip's RK3328 SoC. As the official wiki page puts it, "E for Ethernets". It features the RK3328 SoC, gigabit and fast Ethernet RJ45 ports, both directly served by Ethernet controllers in the SoC, a USB 3.0 host port, a power-only USB type-C port, a 3.5mm headphone jack for audio output, two LEDs, a 40-pin Raspberry Pi style GPIO header, and optional WiFi+BT and PoE header. The board comes in multiple configurations, differing in the amount of onboard RAM, the level of WiFi+BT (none, 802.11n 2.4GHz, or 802.11ac 2.4 GHz & 5 GHz), and whether PoE is supported or not. These variants can all share the same device tree. The USB 2.0 OTG controller is available on the 40-pin header. This is not enabled in the device tree, since it is possible to use it in a host-only configuration, or in OTG mode with an extra pin from the header as the ID pin. The device tree is based on the one of the Rock64, with various parts modified to match the ROCK Pi E, and some parts updated to newer styles, such as the gmac2io node's mdio sub-node. Add a compatible string for the new board. Acked-by: Rob Herring Signed-off-by: Chen-Yu Tsai --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 773fd4c531ed..c3036f95c7bc 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -468,6 +468,11 @@ properties: - const: radxa,rockpi4 - const: rockchip,rk3399 + - description: Radxa ROCK Pi E + items: + - const: radxa,rockpi-e + - const: rockchip,rk3328 + - description: Radxa ROCK Pi N8 items: - const: radxa,rockpi-n8 From patchwork Sun Jan 17 10:07:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 1366444 Return-Path: Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9618AC433E0 for ; Sun, 17 Jan 2021 10:09:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 677782065D for ; Sun, 17 Jan 2021 10:09:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728380AbhAQKIs (ORCPT ); Sun, 17 Jan 2021 05:08:48 -0500 Received: from mail.kernel.org ([198.145.29.99]:43692 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727485AbhAQKIB (ORCPT ); Sun, 17 Jan 2021 05:08:01 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id 8A85F206B2; Sun, 17 Jan 2021 10:07:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1610878040; bh=6Xh0DA4M/ccDjInXDewRVHGdSRxeLB+Ou2/ryXsXw+8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Cyg3QRh5bDUlcyXTfa7kDLxIm7f1nVw//2yhqf2iCCdM2xDHQGZeVPTYQwsje4kg3 mMj2c41DUd1BoYSq0MVBw3nWEdSvqpXjAqawSdyaVGJQ/FqB/jgLs1BlPu+AvO3b+J r0x/CfabJ8y8lf8vG6VLekwkVFgPaL08t4pdsehHWl0vIQD/enDZiJSJY57redh5qk dweQHq0qHwqqYOlLnSSngQiMak5GrDSOkD9Q+wM4p0/ph6Nk1cIzih5oXeu+wE5/mE v4+7aFa/MaNIkmPlL/Ha+RNKUnNVIo7B7QThnvwI5NLRveECg/lCtHy0tFq04aCJlj KwAF4zALu+BBg== Received: by wens.tw (Postfix, from userid 1000) id D02185FBB9; Sun, 17 Jan 2021 18:07:17 +0800 (CST) From: Chen-Yu Tsai To: Rob Herring , Heiko Stuebner Cc: Chen-Yu Tsai , linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 3/3] arm64: dts: rockchip: rk3328: Add Radxa ROCK Pi E Date: Sun, 17 Jan 2021 18:07:10 +0800 Message-Id: <20210117100710.4857-4-wens@kernel.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210117100710.4857-1-wens@kernel.org> References: <20210117100710.4857-1-wens@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Chen-Yu Tsai Radxa ROCK Pi E is a router oriented SBC based on Rockchip's RK3328 SoC. As the official wiki page puts it, "E for Ethernets". It features the RK3328 SoC, gigabit and fast Ethernet RJ45 ports, both directly served by Ethernet controllers in the SoC, a USB 3.0 host port, a power-only USB type-C port, a 3.5mm headphone jack for audio output, two LEDs, a 40-pin Raspberry Pi style GPIO header, and optional WiFi+BT and PoE header. The board comes in multiple configurations, differing in the amount of onboard RAM, the level of WiFi+BT (none, 802.11n 2.4GHz, or 802.11ac 2.4 GHz & 5 GHz), and whether PoE is supported or not. These variants can all share the same device tree. The USB 2.0 OTG controller is available on the 40-pin header. This is not enabled in the device tree, since it is possible to use it in a host-only configuration, or in OTG mode with an extra pin from the header as the ID pin. The device tree is based on the one of the Rock64, with various parts modified to match the ROCK Pi E, and some parts updated to newer styles, such as the gmac2io node's mdio sub-node. Add a new device tree file for the new board. The voltages for the adc-keys were selected to have some tolerances for resistor variances and the ADC itself also causing voltage drops. Since the recover button is the only button on the adc line, this should not cause any issues. Signed-off-by: Chen-Yu Tsai --- Changes since v1: - Dropped comment about LED color - Dropped max-frequency from emmc node - Changed pingroup name from "ethernet-phy" to "ephy" to avoid DT binding check failure - Dropped cap-mmc-highspeed from sdmmc node - Fixed regulator properties to have consistent ordering - Added adc-key for recovery button - Sorted header files --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3328-rock-pi-e.dts | 382 ++++++++++++++++++ 2 files changed, 383 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 622d320ddd13..62d3abc17a24 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -11,6 +11,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-geekbox.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts new file mode 100644 index 000000000000..2d71ca7e429c --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts @@ -0,0 +1,382 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * (C) Copyright 2020 Chen-Yu Tsai + * + * Based on ./rk3328-rock64.dts, which is + * + * Copyright (c) 2017 PINE64 + */ + +/dts-v1/; + +#include +#include +#include +#include + +#include "rk3328.dtsi" + +/ { + model = "Radxa ROCK Pi E"; + compatible = "radxa,rockpi-e", "rockchip,rk3328"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1750000>; + + /* This button is unpopulated out of the factory. */ + button-recovery { + label = "Recovery"; + linux,code = ; + press-threshold-microvolt = <10000>; + }; + }; + + gmac_clkin: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac_clkin"; + #clock-cells = <0>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pin>; + pinctrl-names = "default"; + + led-0 { + color = ; + gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0m1_pin>; + regulator-name = "vcc_sd"; + regulator-boot-on; + vin-supply = <&vcc_io>; + }; + + vcc_host_5v: vcc-host-5v-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb30_host_drv>; + enable-active-high; + regulator-name = "vcc_host_5v"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc_wifi: vcc-wifi-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_en>; + regulator-name = "vcc_wifi"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_io>; + }; +}; + +&analog_sound { + status = "okay"; +}; + +&codec { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc18_emmc>; + status = "okay"; +}; + +&gmac2io { + assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; + assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; + clock_in_out = "input"; + phy-handle = <&rtl8211e>; + phy-mode = "rgmii"; + phy-supply = <&vcc_io>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmiim1_pins>; + snps,aal; + snps,rxpbl = <0x4>; + snps,txpbl = <0x4>; + tx_delay = <0x26>; + rx_delay = <0x11>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + rtl8211e: ethernet-phy@1 { + reg = <1>; + pinctrl-0 = <ð_phy_int_pin>, <ð_phy_reset_pin>; + pinctrl-names = "default"; + interrupt-parent = <&gpio1>; + interrupts = <24 IRQ_TYPE_LEVEL_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <50000>; + reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gmac2phy { + pinctrl-names = "default"; + pinctrl-0 = <&fephyled_linkm1>, <&fephyled_rxm1>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + rk805: pmic@18 { + compatible = "rockchip,rk805"; + reg = <0x18>; + interrupt-parent = <&gpio2>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk805-clkout2"; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_io>; + vcc6-supply = <&vcc_sys>; + + regulators { + vdd_log: DCDC_REG1 { + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-name = "vcc_io"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_18: LDO_REG1 { + regulator-name = "vcc_18"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc18_emmc: LDO_REG2 { + regulator-name = "vcc18_emmc"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_10: LDO_REG3 { + regulator-name = "vdd_10"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + }; + }; +}; + +&i2s1 { + status = "okay"; +}; + +&io_domains { + pmuio-supply = <&vcc_io>; + vccio1-supply = <&vcc_io>; + vccio2-supply = <&vcc18_emmc>; + vccio3-supply = <&vcc_io>; + vccio4-supply = <&vcc_io>; + vccio5-supply = <&vcc_io>; + vccio6-supply = <&vcc_io>; + status = "okay"; +}; + +&pinctrl { + ephy { + eth_phy_int_pin: eth-phy-int-pin { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + eth_phy_reset_pin: eth-phy-reset-pin { + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + leds { + led_pin: led-pin { + rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb3 { + usb30_host_drv: usb30-host-drv { + rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_en: wifi-en { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>; + vmmc-supply = <&vcc_sd>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_18>; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy { + status = "okay"; +}; + +&u2phy_host { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +};