(no subject)

[Lux Aliaga]

Introduce Universal Flash Storage support on SM6125 and add support for the Xiaomi Mi A3 based on the former platform.

Changes since v6:
- Add struct for v3-660 UFS PHY offsets and modify sm6115 UFS PHY to use it
- Set ufs_mem_phy reg size to 0xdb8 in sm6125.dtsi
- Drop "#address-cells" and "#size-cells" properties on reserved-memory node in xiaomi-laurel-sprout dts
- Move "status" last on &pon_resin node in xiaomi-laurel-sprout dts
- Modify "&pm6125_gpio" pointer to "&pm6125_gpios" in xiaomi-laurel-sprout dts

v6: https://lore.kernel.org/linux-devicetree/20230108195336.388349-1-they@mint.lgbt/
v5: https://lore.kernel.org/linux-devicetree/20221231222420.75233-2-they@mint.lgbt/

[PATCH v7 1/6] dt-bindings: ufs: qcom: Add SM6125 compatible string

[Lux Aliaga]

Document the compatible for UFS found on the SM6125.

Signed-off-by: Lux Aliaga <they@mint.lgbt>
Reviewed-by: Martin Botka <martin.botka@somainline.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 Documentation/devicetree/bindings/ufs/qcom,ufs.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
index b517d76215e3..42422f3471b3 100644
--- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
+++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
@@ -29,6 +29,7 @@ properties:
           - qcom,sc8280xp-ufshc
           - qcom,sdm845-ufshc
           - qcom,sm6115-ufshc
+          - qcom,sm6125-ufshc
           - qcom,sm6350-ufshc
           - qcom,sm8150-ufshc
           - qcom,sm8250-ufshc
@@ -185,6 +186,7 @@ allOf:
           contains:
             enum:
               - qcom,sm6115-ufshc
+              - qcom,sm6125-ufshc
     then:
       properties:
         clocks:
-- 
2.39.2

[PATCH v7 2/6] dt-bindings: phy: Add QMP UFS PHY compatible for SM6125

[Lux Aliaga]

Document the QMP UFS PHY compatible for SM6125.

Signed-off-by: Lux Aliaga <they@mint.lgbt>
Reviewed-by: Martin Botka <martin.botka@somainline.org>
Acked-by: Dhruva Gole <d-gole@ti.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
---
 .../devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml       | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
index dde86a19f792..a7af57931f32 100644
--- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
@@ -17,6 +17,7 @@ properties:
   compatible:
     enum:
       - qcom,sc8280xp-qmp-ufs-phy
+      - qcom,sm6125-qmp-ufs-phy
 
   reg:
     maxItems: 1
-- 
2.39.2

[PATCH v7 3/6] phy: qcom-qmp: Add SM6125 UFS PHY support

[Lux Aliaga]

The SM6125 UFS PHY is compatible with the one from SM6115. Add a
compatible for it and modify the config from SM6115 to make them
compatible with the SC8280XP binding

Signed-off-by: Lux Aliaga <they@mint.lgbt>
Reviewed-by: Martin Botka <martin.botka@somainline.org>
---
 drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index 318eea35b972..44c29fdfc551 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -620,6 +620,13 @@ static const char * const qmp_phy_vreg_l[] = {
 	"vdda-phy", "vdda-pll",
 };
 
+static const struct qmp_ufs_offsets qmp_ufs_offsets_v3_660 = {
+	.serdes		= 0,
+	.pcs		= 0xc00,
+	.tx		= 0x400,
+	.rx		= 0x600,
+};
+
 static const struct qmp_ufs_offsets qmp_ufs_offsets_v5 = {
 	.serdes		= 0,
 	.pcs		= 0xc00,
@@ -693,6 +700,8 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
 static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
 	.lanes			= 1,
 
+	.offsets		= &qmp_ufs_offsets_v3_660,
+
 	.serdes_tbl		= sm6115_ufsphy_serdes_tbl,
 	.serdes_tbl_num		= ARRAY_SIZE(sm6115_ufsphy_serdes_tbl),
 	.tx_tbl			= sm6115_ufsphy_tx_tbl,
@@ -1172,6 +1181,9 @@ static const struct of_device_id qmp_ufs_of_match_table[] = {
 	}, {
 		.compatible = "qcom,sm6115-qmp-ufs-phy",
 		.data = &sm6115_ufsphy_cfg,
+	}, {
+		.compatible = "qcom,sm6125-qmp-ufs-phy",
+		.data = &sm6115_ufsphy_cfg,
 	}, {
 		.compatible = "qcom,sm6350-qmp-ufs-phy",
 		.data = &sdm845_ufsphy_cfg,
-- 
2.39.2

[PATCH v7 4/6] arm64: dts: qcom: sm6125: Add UFS nodes

[Lux Aliaga]

Adds a UFS host controller node and its corresponding PHY to
the sm6125 platform.

Signed-off-by: Lux Aliaga <they@mint.lgbt>
---
 arch/arm64/boot/dts/qcom/sm6125.dtsi | 62 ++++++++++++++++++++++++++++
 1 file changed, 62 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
index df5453fcf2b9..7384d88f44cc 100644
--- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
@@ -511,6 +511,68 @@ sdhc_2: mmc@4784000 {
 			status = "disabled";
 		};
 
+		ufs_mem_hc: ufs@4804000 {
+			compatible = "qcom,sm6125-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
+			reg = <0x04804000 0x3000>, <0x04810000 0x8000>;
+			reg-names = "std", "ice";
+			interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+
+			clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
+				 <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>,
+				 <&gcc GCC_UFS_PHY_AHB_CLK>,
+				 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+				 <&rpmcc RPM_SMD_XO_CLK_SRC>,
+				 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+				 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
+				 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+			clock-names = "core_clk",
+				      "bus_aggr_clk",
+				      "iface_clk",
+				      "core_clk_unipro",
+				      "ref_clk",
+				      "tx_lane0_sync_clk",
+				      "rx_lane0_sync_clk",
+				      "ice_core_clk";
+			freq-table-hz = <50000000 240000000>,
+					<0 0>,
+					<0 0>,
+					<37500000 150000000>,
+					<0 0>,
+					<0 0>,
+					<0 0>,
+					<75000000 300000000>;
+
+			resets = <&gcc GCC_UFS_PHY_BCR>;
+			reset-names = "rst";
+			#reset-cells = <1>;
+
+			phys = <&ufs_mem_phy>;
+			phy-names = "ufsphy";
+
+			lanes-per-direction = <1>;
+
+			iommus = <&apps_smmu 0x200 0x0>;
+
+			status = "disabled";
+		};
+
+		ufs_mem_phy: phy@4807000 {
+			compatible = "qcom,sm6125-qmp-ufs-phy";
+			reg = <0x04807000 0xdb8>;
+
+			clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
+			clock-names = "ref", "ref_aux";
+
+			resets = <&ufs_mem_hc 0>;
+			reset-names = "ufsphy";
+
+			power-domains = <&gcc UFS_PHY_GDSC>;
+
+			#phy-cells = <0>;
+
+			status = "disabled";
+		};
+
 		gpi_dma0: dma-controller@4a00000 {
 			compatible = "qcom,sm6125-gpi-dma", "qcom,sdm845-gpi-dma";
 			reg = <0x04a00000 0x60000>;
-- 
2.39.2

Re: [PATCH v7 1/6] dt-bindings: ufs: qcom: Add SM6125 compatible string

[Lux Aliaga]

On 06/03/2023 13:52, Lux Aliaga wrote:
> Document the compatible for UFS found on the SM6125.
>
> Signed-off-by: Lux Aliaga <they@mint.lgbt>
> Reviewed-by: Martin Botka <martin.botka@somainline.org>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
>   Documentation/devicetree/bindings/ufs/qcom,ufs.yaml | 2 ++
>   1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
> index b517d76215e3..42422f3471b3 100644
> --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
> +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
> @@ -29,6 +29,7 @@ properties:
>             - qcom,sc8280xp-ufshc
>             - qcom,sdm845-ufshc
>             - qcom,sm6115-ufshc
> +          - qcom,sm6125-ufshc
>             - qcom,sm6350-ufshc
>             - qcom,sm8150-ufshc
>             - qcom,sm8250-ufshc
> @@ -185,6 +186,7 @@ allOf:
>             contains:
>               enum:
>                 - qcom,sm6115-ufshc
> +              - qcom,sm6125-ufshc
>       then:
>         properties:
>           clocks:
I have to apologize. I worked on a changelog for this patchset but I 
skipped the subject header, therefore it didn't send, and as I realized 
this I interrupted the process, leaving the patchset incomplete. I'll 
retry sending it, this time correctly.

-- 
Lux Aliaga
https://nixgoat.me/

Re: [PATCH v7 1/6] dt-bindings: ufs: qcom: Add SM6125 compatible string

[Konrad Dybcio]

On 6.03.2023 18:01, Lux Aliaga wrote:
> 
> On 06/03/2023 13:52, Lux Aliaga wrote:
>> Document the compatible for UFS found on the SM6125.
>>
>> Signed-off-by: Lux Aliaga <they@mint.lgbt>
>> Reviewed-by: Martin Botka <martin.botka@somainline.org>
>> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>> ---
>>   Documentation/devicetree/bindings/ufs/qcom,ufs.yaml | 2 ++
>>   1 file changed, 2 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
>> index b517d76215e3..42422f3471b3 100644
>> --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
>> +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
>> @@ -29,6 +29,7 @@ properties:
>>             - qcom,sc8280xp-ufshc
>>             - qcom,sdm845-ufshc
>>             - qcom,sm6115-ufshc
>> +          - qcom,sm6125-ufshc
>>             - qcom,sm6350-ufshc
>>             - qcom,sm8150-ufshc
>>             - qcom,sm8250-ufshc
>> @@ -185,6 +186,7 @@ allOf:
>>             contains:
>>               enum:
>>                 - qcom,sm6115-ufshc
>> +              - qcom,sm6125-ufshc
>>       then:
>>         properties:
>>           clocks:
> I have to apologize. I worked on a changelog for this patchset but I skipped the subject header, therefore it didn't send, and as I realized this I interrupted the process, leaving the patchset incomplete. I'll retry sending it, this time correctly.
Happens, next time resend it with a RESEND prefix, e.g. [RESEND PATCH 1/2]

Konrad
> 

Re: [PATCH v7 1/6] dt-bindings: ufs: qcom: Add SM6125 compatible string

[Lux Aliaga]

On 3/6/2023 14:09, Konrad Dybcio wrote:

>
> On 6.03.2023 18:01, Lux Aliaga wrote:
>> On 06/03/2023 13:52, Lux Aliaga wrote:
>>> Document the compatible for UFS found on the SM6125.
>>>
>>> Signed-off-by: Lux Aliaga <they@mint.lgbt>
>>> Reviewed-by: Martin Botka <martin.botka@somainline.org>
>>> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>>> ---
>>>    Documentation/devicetree/bindings/ufs/qcom,ufs.yaml | 2 ++
>>>    1 file changed, 2 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
>>> index b517d76215e3..42422f3471b3 100644
>>> --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
>>> +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
>>> @@ -29,6 +29,7 @@ properties:
>>>              - qcom,sc8280xp-ufshc
>>>              - qcom,sdm845-ufshc
>>>              - qcom,sm6115-ufshc
>>> +          - qcom,sm6125-ufshc
>>>              - qcom,sm6350-ufshc
>>>              - qcom,sm8150-ufshc
>>>              - qcom,sm8250-ufshc
>>> @@ -185,6 +186,7 @@ allOf:
>>>              contains:
>>>                enum:
>>>                  - qcom,sm6115-ufshc
>>> +              - qcom,sm6125-ufshc
>>>        then:
>>>          properties:
>>>            clocks:
>> I have to apologize. I worked on a changelog for this patchset but I skipped the subject header, therefore it didn't send, and as I realized this I interrupted the process, leaving the patchset incomplete. I'll retry sending it, this time correctly.
> Happens, next time resend it with a RESEND prefix, e.g. [RESEND PATCH 1/2]
>
> Konrad

Thank you! Will take this into consideration for the future. I received 
this email after I resent the patchset, so that's why I didn't add the 
prefix.

-- 
Lux Aliaga
https://nixgoat.me/

Re: [PATCH v7 3/6] phy: qcom-qmp: Add SM6125 UFS PHY support

[Johan Hovold]

On Wed, Mar 08, 2023 at 08:37:48AM -0300, Lux Aliaga wrote:
> On 8 March 2023 08:23:57 GMT-03:00, Johan Hovold <johan@kernel.org> wrote:

> >It seems a previous version of this patch was merged almost two months
> >ago.
> >
> >	9b9e29af984c ("phy: qcom-qmp: Add SM6125 UFS PHY support")
> >
> >Not sure what failed here.

> Yes, but it received some comments regarding using v5 offsets instead
> of v3-660. I could spin off this change into a new patch if necessary.

Once a patch has been applied, you generally need to do any further
changes incrementally on top.

It seems Dmitry renamed the struct himself after the patch was applied
in this case.

Johan

Re: [PATCH v7 3/6] phy: qcom-qmp: Add SM6125 UFS PHY support

[Lux Aliaga]

On 8 March 2023 08:23:57 GMT-03:00, Johan Hovold <johan@kernel.org> wrote:
>On Wed, Mar 08, 2023 at 12:15:39PM +0100, Konrad Dybcio wrote:
>> 
>> 
>> On 8.03.2023 12:02, Johan Hovold wrote:
>> > On Wed, Mar 08, 2023 at 11:09:48AM +0100, Konrad Dybcio wrote:
>> >>
>> >>
>> >> On 6.03.2023 18:08, Lux Aliaga wrote:
>> >>> The SM6125 UFS PHY is compatible with the one from SM6115. Add a
>> >>> compatible for it and modify the config from SM6115 to make them
>> >>> compatible with the SC8280XP binding
>> >>>
>> >>> Signed-off-by: Lux Aliaga <they@mint.lgbt>
>> >>> Reviewed-by: Martin Botka <martin.botka@somainline.org>
>> >>> ---
>> >>>  drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 12 ++++++++++++
>> >>>  1 file changed, 12 insertions(+)
>> >>>
>> >>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>> >>> index 318eea35b972..44c29fdfc551 100644
>> >>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>> >>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>> >>> @@ -620,6 +620,13 @@ static const char * const qmp_phy_vreg_l[] = {
>> >>>  	"vdda-phy", "vdda-pll",
>> >>>  };
>> >>>  
>> >>> +static const struct qmp_ufs_offsets qmp_ufs_offsets_v3_660 = {
>> >>> +	.serdes		= 0,
>> >>> +	.pcs		= 0xc00,
>> >>> +	.tx		= 0x400,
>> >>> +	.rx		= 0x600,
>> >>> +};
>> >>> +
>> >>>  static const struct qmp_ufs_offsets qmp_ufs_offsets_v5 = {
>> >>>  	.serdes		= 0,
>> >>>  	.pcs		= 0xc00,
>> >>> @@ -693,6 +700,8 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
>> >>>  static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
>> >>>  	.lanes			= 1,
>> >>>  
>> >>> +	.offsets		= &qmp_ufs_offsets_v3_660,
>> >> Will this not trigger OOB r/w for the users of qcom,sm6115-smp-ufs-phy
>> >> which specify the regions separately (old binding style)?
>> > 
>> > No, that should work fine.
>> So do you think the SM6115 binding could be updated too? Or should
>> we keep it as-is for ABI purposes?..
>
>They could be and the possibility has been raised. I think it may be
>more important to convert the old combo-phy binding (it's on my list,
>but I keep getting preempted), but at some point we can get rid of the
>legacy UFS binding as well.
>
>> > But looks like this series needs to be rebased on 6.3-rc1 as these
>> > offsets are now already set in mainline.
>> ..Or did you do that already and I can't find it?
>
>It seems a previous version of this patch was merged almost two months
>ago.
>
>	9b9e29af984c ("phy: qcom-qmp: Add SM6125 UFS PHY support")
>
>Not sure what failed here.
>
>Johan
Yes, but it received some comments regarding using v5 offsets instead of v3-660. I could spin off this change into a new patch if necessary.

Re: [PATCH v7 3/6] phy: qcom-qmp: Add SM6125 UFS PHY support

[Konrad Dybcio]

On 8.03.2023 12:23, Johan Hovold wrote:
> On Wed, Mar 08, 2023 at 12:15:39PM +0100, Konrad Dybcio wrote:
>>
>>
>> On 8.03.2023 12:02, Johan Hovold wrote:
>>> On Wed, Mar 08, 2023 at 11:09:48AM +0100, Konrad Dybcio wrote:
>>>>
>>>>
>>>> On 6.03.2023 18:08, Lux Aliaga wrote:
>>>>> The SM6125 UFS PHY is compatible with the one from SM6115. Add a
>>>>> compatible for it and modify the config from SM6115 to make them
>>>>> compatible with the SC8280XP binding
>>>>>
>>>>> Signed-off-by: Lux Aliaga <they@mint.lgbt>
>>>>> Reviewed-by: Martin Botka <martin.botka@somainline.org>
>>>>> ---
>>>>>  drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 12 ++++++++++++
>>>>>  1 file changed, 12 insertions(+)
>>>>>
>>>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>>>>> index 318eea35b972..44c29fdfc551 100644
>>>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>>>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>>>>> @@ -620,6 +620,13 @@ static const char * const qmp_phy_vreg_l[] = {
>>>>>  	"vdda-phy", "vdda-pll",
>>>>>  };
>>>>>  
>>>>> +static const struct qmp_ufs_offsets qmp_ufs_offsets_v3_660 = {
>>>>> +	.serdes		= 0,
>>>>> +	.pcs		= 0xc00,
>>>>> +	.tx		= 0x400,
>>>>> +	.rx		= 0x600,
>>>>> +};
>>>>> +
>>>>>  static const struct qmp_ufs_offsets qmp_ufs_offsets_v5 = {
>>>>>  	.serdes		= 0,
>>>>>  	.pcs		= 0xc00,
>>>>> @@ -693,6 +700,8 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
>>>>>  static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
>>>>>  	.lanes			= 1,
>>>>>  
>>>>> +	.offsets		= &qmp_ufs_offsets_v3_660,
>>>> Will this not trigger OOB r/w for the users of qcom,sm6115-smp-ufs-phy
>>>> which specify the regions separately (old binding style)?
>>>
>>> No, that should work fine.
>> So do you think the SM6115 binding could be updated too? Or should
>> we keep it as-is for ABI purposes?..
> 
> They could be and the possibility has been raised. I think it may be
> more important to convert the old combo-phy binding (it's on my list,
> but I keep getting preempted), but at some point we can get rid of the
> legacy UFS binding as well.
Okay sounds good!

> 
>>> But looks like this series needs to be rebased on 6.3-rc1 as these
>>> offsets are now already set in mainline.
>> ..Or did you do that already and I can't find it?
> 
> It seems a previous version of this patch was merged almost two months
> ago.
> 
> 	9b9e29af984c ("phy: qcom-qmp: Add SM6125 UFS PHY support")
> 
> Not sure what failed here.
My eyes :)

Konrad
> 
> Johan

Re: [PATCH v7 3/6] phy: qcom-qmp: Add SM6125 UFS PHY support

[Johan Hovold]

On Wed, Mar 08, 2023 at 12:15:39PM +0100, Konrad Dybcio wrote:
> 
> 
> On 8.03.2023 12:02, Johan Hovold wrote:
> > On Wed, Mar 08, 2023 at 11:09:48AM +0100, Konrad Dybcio wrote:
> >>
> >>
> >> On 6.03.2023 18:08, Lux Aliaga wrote:
> >>> The SM6125 UFS PHY is compatible with the one from SM6115. Add a
> >>> compatible for it and modify the config from SM6115 to make them
> >>> compatible with the SC8280XP binding
> >>>
> >>> Signed-off-by: Lux Aliaga <they@mint.lgbt>
> >>> Reviewed-by: Martin Botka <martin.botka@somainline.org>
> >>> ---
> >>>  drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 12 ++++++++++++
> >>>  1 file changed, 12 insertions(+)
> >>>
> >>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> >>> index 318eea35b972..44c29fdfc551 100644
> >>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> >>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> >>> @@ -620,6 +620,13 @@ static const char * const qmp_phy_vreg_l[] = {
> >>>  	"vdda-phy", "vdda-pll",
> >>>  };
> >>>  
> >>> +static const struct qmp_ufs_offsets qmp_ufs_offsets_v3_660 = {
> >>> +	.serdes		= 0,
> >>> +	.pcs		= 0xc00,
> >>> +	.tx		= 0x400,
> >>> +	.rx		= 0x600,
> >>> +};
> >>> +
> >>>  static const struct qmp_ufs_offsets qmp_ufs_offsets_v5 = {
> >>>  	.serdes		= 0,
> >>>  	.pcs		= 0xc00,
> >>> @@ -693,6 +700,8 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
> >>>  static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
> >>>  	.lanes			= 1,
> >>>  
> >>> +	.offsets		= &qmp_ufs_offsets_v3_660,
> >> Will this not trigger OOB r/w for the users of qcom,sm6115-smp-ufs-phy
> >> which specify the regions separately (old binding style)?
> > 
> > No, that should work fine.
> So do you think the SM6115 binding could be updated too? Or should
> we keep it as-is for ABI purposes?..

They could be and the possibility has been raised. I think it may be
more important to convert the old combo-phy binding (it's on my list,
but I keep getting preempted), but at some point we can get rid of the
legacy UFS binding as well.

> > But looks like this series needs to be rebased on 6.3-rc1 as these
> > offsets are now already set in mainline.
> ..Or did you do that already and I can't find it?

It seems a previous version of this patch was merged almost two months
ago.

	9b9e29af984c ("phy: qcom-qmp: Add SM6125 UFS PHY support")

Not sure what failed here.

Johan

Re: [PATCH v7 3/6] phy: qcom-qmp: Add SM6125 UFS PHY support

[Konrad Dybcio]

On 8.03.2023 12:02, Johan Hovold wrote:
> On Wed, Mar 08, 2023 at 11:09:48AM +0100, Konrad Dybcio wrote:
>>
>>
>> On 6.03.2023 18:08, Lux Aliaga wrote:
>>> The SM6125 UFS PHY is compatible with the one from SM6115. Add a
>>> compatible for it and modify the config from SM6115 to make them
>>> compatible with the SC8280XP binding
>>>
>>> Signed-off-by: Lux Aliaga <they@mint.lgbt>
>>> Reviewed-by: Martin Botka <martin.botka@somainline.org>
>>> ---
>>>  drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 12 ++++++++++++
>>>  1 file changed, 12 insertions(+)
>>>
>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>>> index 318eea35b972..44c29fdfc551 100644
>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>>> @@ -620,6 +620,13 @@ static const char * const qmp_phy_vreg_l[] = {
>>>  	"vdda-phy", "vdda-pll",
>>>  };
>>>  
>>> +static const struct qmp_ufs_offsets qmp_ufs_offsets_v3_660 = {
>>> +	.serdes		= 0,
>>> +	.pcs		= 0xc00,
>>> +	.tx		= 0x400,
>>> +	.rx		= 0x600,
>>> +};
>>> +
>>>  static const struct qmp_ufs_offsets qmp_ufs_offsets_v5 = {
>>>  	.serdes		= 0,
>>>  	.pcs		= 0xc00,
>>> @@ -693,6 +700,8 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
>>>  static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
>>>  	.lanes			= 1,
>>>  
>>> +	.offsets		= &qmp_ufs_offsets_v3_660,
>> Will this not trigger OOB r/w for the users of qcom,sm6115-smp-ufs-phy
>> which specify the regions separately (old binding style)?
> 
> No, that should work fine.
So do you think the SM6115 binding could be updated too? Or should
we keep it as-is for ABI purposes?..

> 
> But looks like this series needs to be rebased on 6.3-rc1 as these
> offsets are now already set in mainline.
..Or did you do that already and I can't find it?

Konrad
> 
> Johan

Re: [PATCH v7 3/6] phy: qcom-qmp: Add SM6125 UFS PHY support

[Johan Hovold]

On Wed, Mar 08, 2023 at 11:09:48AM +0100, Konrad Dybcio wrote:
> 
> 
> On 6.03.2023 18:08, Lux Aliaga wrote:
> > The SM6125 UFS PHY is compatible with the one from SM6115. Add a
> > compatible for it and modify the config from SM6115 to make them
> > compatible with the SC8280XP binding
> > 
> > Signed-off-by: Lux Aliaga <they@mint.lgbt>
> > Reviewed-by: Martin Botka <martin.botka@somainline.org>
> > ---
> >  drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 12 ++++++++++++
> >  1 file changed, 12 insertions(+)
> > 
> > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > index 318eea35b972..44c29fdfc551 100644
> > --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > @@ -620,6 +620,13 @@ static const char * const qmp_phy_vreg_l[] = {
> >  	"vdda-phy", "vdda-pll",
> >  };
> >  
> > +static const struct qmp_ufs_offsets qmp_ufs_offsets_v3_660 = {
> > +	.serdes		= 0,
> > +	.pcs		= 0xc00,
> > +	.tx		= 0x400,
> > +	.rx		= 0x600,
> > +};
> > +
> >  static const struct qmp_ufs_offsets qmp_ufs_offsets_v5 = {
> >  	.serdes		= 0,
> >  	.pcs		= 0xc00,
> > @@ -693,6 +700,8 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
> >  static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
> >  	.lanes			= 1,
> >  
> > +	.offsets		= &qmp_ufs_offsets_v3_660,
> Will this not trigger OOB r/w for the users of qcom,sm6115-smp-ufs-phy
> which specify the regions separately (old binding style)?

No, that should work fine.

But looks like this series needs to be rebased on 6.3-rc1 as these
offsets are now already set in mainline.

Johan

Re: [PATCH v7 3/6] phy: qcom-qmp: Add SM6125 UFS PHY support

[Konrad Dybcio]

On 6.03.2023 18:08, Lux Aliaga wrote:
> The SM6125 UFS PHY is compatible with the one from SM6115. Add a
> compatible for it and modify the config from SM6115 to make them
> compatible with the SC8280XP binding
> 
> Signed-off-by: Lux Aliaga <they@mint.lgbt>
> Reviewed-by: Martin Botka <martin.botka@somainline.org>
> ---
>  drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> index 318eea35b972..44c29fdfc551 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> @@ -620,6 +620,13 @@ static const char * const qmp_phy_vreg_l[] = {
>  	"vdda-phy", "vdda-pll",
>  };
>  
> +static const struct qmp_ufs_offsets qmp_ufs_offsets_v3_660 = {
> +	.serdes		= 0,
> +	.pcs		= 0xc00,
> +	.tx		= 0x400,
> +	.rx		= 0x600,
> +};
> +
>  static const struct qmp_ufs_offsets qmp_ufs_offsets_v5 = {
>  	.serdes		= 0,
>  	.pcs		= 0xc00,
> @@ -693,6 +700,8 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
>  static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
>  	.lanes			= 1,
>  
> +	.offsets		= &qmp_ufs_offsets_v3_660,
Will this not trigger OOB r/w for the users of qcom,sm6115-smp-ufs-phy
which specify the regions separately (old binding style)?

Konrad
> +
>  	.serdes_tbl		= sm6115_ufsphy_serdes_tbl,
>  	.serdes_tbl_num		= ARRAY_SIZE(sm6115_ufsphy_serdes_tbl),
>  	.tx_tbl			= sm6115_ufsphy_tx_tbl,
> @@ -1172,6 +1181,9 @@ static const struct of_device_id qmp_ufs_of_match_table[] = {
>  	}, {
>  		.compatible = "qcom,sm6115-qmp-ufs-phy",
>  		.data = &sm6115_ufsphy_cfg,
> +	}, {
> +		.compatible = "qcom,sm6125-qmp-ufs-phy",
> +		.data = &sm6115_ufsphy_cfg,
>  	}, {
>  		.compatible = "qcom,sm6350-qmp-ufs-phy",
>  		.data = &sdm845_ufsphy_cfg,

[PATCH v7 3/6] phy: qcom-qmp: Add SM6125 UFS PHY support

[Lux Aliaga]

The SM6125 UFS PHY is compatible with the one from SM6115. Add a
compatible for it and modify the config from SM6115 to make them
compatible with the SC8280XP binding

Signed-off-by: Lux Aliaga <they@mint.lgbt>
Reviewed-by: Martin Botka <martin.botka@somainline.org>
---
 drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index 318eea35b972..44c29fdfc551 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -620,6 +620,13 @@ static const char * const qmp_phy_vreg_l[] = {
 	"vdda-phy", "vdda-pll",
 };
 
+static const struct qmp_ufs_offsets qmp_ufs_offsets_v3_660 = {
+	.serdes		= 0,
+	.pcs		= 0xc00,
+	.tx		= 0x400,
+	.rx		= 0x600,
+};
+
 static const struct qmp_ufs_offsets qmp_ufs_offsets_v5 = {
 	.serdes		= 0,
 	.pcs		= 0xc00,
@@ -693,6 +700,8 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
 static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
 	.lanes			= 1,
 
+	.offsets		= &qmp_ufs_offsets_v3_660,
+
 	.serdes_tbl		= sm6115_ufsphy_serdes_tbl,
 	.serdes_tbl_num		= ARRAY_SIZE(sm6115_ufsphy_serdes_tbl),
 	.tx_tbl			= sm6115_ufsphy_tx_tbl,
@@ -1172,6 +1181,9 @@ static const struct of_device_id qmp_ufs_of_match_table[] = {
 	}, {
 		.compatible = "qcom,sm6115-qmp-ufs-phy",
 		.data = &sm6115_ufsphy_cfg,
+	}, {
+		.compatible = "qcom,sm6125-qmp-ufs-phy",
+		.data = &sm6115_ufsphy_cfg,
 	}, {
 		.compatible = "qcom,sm6350-qmp-ufs-phy",
 		.data = &sdm845_ufsphy_cfg,
-- 
2.39.2