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Tue, 7 Sep 2021 22:58:53 +0000 (UTC) Received: from mail.codeaurora.org (localhost.localdomain [127.0.0.1]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: abhinavk) by smtp.codeaurora.org (Postfix) with ESMTPSA id C9FACC4338F; Tue, 7 Sep 2021 22:58:52 +0000 (UTC) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit Date: Tue, 07 Sep 2021 15:58:52 -0700 From: abhinavk@codeaurora.org To: Marijn Suijten Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, AngeloGioacchino Del Regno , Konrad Dybcio , Martin Botka , Jami Kettunen , Pavel Dubrova , Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Dmitry Baryshkov , Jonathan Marek , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] drm/msm/dsi: Use division result from div_u64_rem in 7nm and 14nm PLL In-Reply-To: <20210906202535.824233-1-marijn.suijten@somainline.org> References: <20210906202535.824233-1-marijn.suijten@somainline.org> Message-ID: <37d3d27f56787ebe608121ce05bb2ad0@codeaurora.org> X-Sender: abhinavk@codeaurora.org User-Agent: Roundcube Webmail/1.3.9 Precedence: bulk List-ID: X-Mailing-List: phone-devel@vger.kernel.org On 2021-09-06 13:25, Marijn Suijten wrote: > div_u64_rem provides the result of the divison and additonally the > remainder; don't use this function to solely calculate the remainder > while calculating the division again with div_u64. > > A similar improvement was applied earlier to the 10nm pll in > 5c191fef4ce2 ("drm/msm/dsi_pll_10nm: Fix dividing the same numbers > twice"). > > Signed-off-by: Marijn Suijten Reviewed-by: Abhinav Kumar > --- > drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 4 +--- > drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 4 +--- > 2 files changed, 2 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c > b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c > index 3c1e2106d962..8905f365c932 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c > @@ -213,9 +213,7 @@ static void pll_14nm_dec_frac_calc(struct > dsi_pll_14nm *pll, struct dsi_pll_conf > DBG("vco_clk_rate=%lld ref_clk_rate=%lld", vco_clk_rate, fref); > > dec_start_multiple = div_u64(vco_clk_rate * multiplier, fref); > - div_u64_rem(dec_start_multiple, multiplier, &div_frac_start); > - > - dec_start = div_u64(dec_start_multiple, multiplier); > + dec_start = div_u64_rem(dec_start_multiple, multiplier, > &div_frac_start); > > pconf->dec_start = (u32)dec_start; > pconf->div_frac_start = div_frac_start; > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > index c77c30628cca..1a5abbd9fb76 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > @@ -114,9 +114,7 @@ static void dsi_pll_calc_dec_frac(struct > dsi_pll_7nm *pll, struct dsi_pll_config > > multiplier = 1 << FRAC_BITS; > dec_multiple = div_u64(pll_freq * multiplier, divider); > - div_u64_rem(dec_multiple, multiplier, &frac); > - > - dec = div_u64(dec_multiple, multiplier); > + dec = div_u64_rem(dec_multiple, multiplier, &frac); > > if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1)) > config->pll_clock_inverters = 0x28;