From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0976DC433FE for ; Sat, 16 Oct 2021 15:09:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CE96561248 for ; Sat, 16 Oct 2021 15:09:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237078AbhJPPMF (ORCPT ); Sat, 16 Oct 2021 11:12:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45196 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237177AbhJPPME (ORCPT ); Sat, 16 Oct 2021 11:12:04 -0400 Received: from mail-qk1-x729.google.com (mail-qk1-x729.google.com [IPv6:2607:f8b0:4864:20::729]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 24B01C061767 for ; Sat, 16 Oct 2021 08:09:56 -0700 (PDT) Received: by mail-qk1-x729.google.com with SMTP id t63so11311702qkf.1 for ; Sat, 16 Oct 2021 08:09:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=ic2B3qAcwXa3Bb0xn0FSuPPQc9LYrHNTOr5kbu049Qc=; b=ZYHCANlUN15by7s7UXXFcFKlreoz0ZiVqI4I2ONz0twA5CNDE/GG6zJ9No+7FvohpD lJszz43Nr/keKxSC8UdoOSQKsxNowDAS0GMhuleCRrIQPRjtSPiPhBmxg0d/uRwrCBcR GGxVwxP/nF4V1cdqTpixvCyHN0ejejeH6q4gWm0fW2GT6NUwkmdm+Kbwl4YLtRWcIKHc ubJuHiLbFjxsg22t+pJWnGtXeRrsQFKRnp7Reu04QuRZD1z3eCnaaMoNixxyCHyRCZUz m22l5BcpZv6MzNTfTxHIH+/t6QwwKBFEaiCAoZwlJdLbjOGToKRddNJos8F//crpmc+E bQUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=ic2B3qAcwXa3Bb0xn0FSuPPQc9LYrHNTOr5kbu049Qc=; b=2M6iSkrW7kO1h/YPhvZSprtgk09IQRE2df3fvEcVOseVDCpGdCr6HZoSfi2y0TCAXt SnR6M9fTTiXzL2vPE8YSg8WCFxt0vc3FkHnGOrGLuy0bj889wVL6Kt2Siwnopod2obJp LDP6W1u/N7cuYuFradYxWOxjNkXDvw5THGP2hUQ5oRQWI1mQhQ6Fh2L5sSOkgCyy/NWH DemJxZIdriqOPge08JF2eEE0vXf5W/yuroQbxZYrjUUNsCXca92hPDGLY/b9oIPJEE0p vBFqaczqW/92jVbe797erUK7IuBTaPhS6sja1B3JWkcxbjeMjlOBRHDFCYl+g1wKV1rK To8w== X-Gm-Message-State: AOAM532qOOEbOJRa5eCAoX+IR17xf2w2xeNbJ4B41KXm8BYRS0Bvu07l 7zDzj1/if9SyQ82nfqMwz/Cfga7yd0XXxjigYdYjwA== X-Google-Smtp-Source: ABdhPJxV8nVMmu9V10uCeG5Lw0KNhKIjiUhuuUIkqH4ZK83pIFkcbD6pd7PLhPz4YWBYcjHdUOXP70Pnq+vCC5VHtOA= X-Received: by 2002:ae9:d842:: with SMTP id u63mr15066970qkf.44.1634396995049; Sat, 16 Oct 2021 08:09:55 -0700 (PDT) MIME-Version: 1.0 References: <20211014083016.137441-1-y.oudjana@protonmail.com> <20211014083016.137441-8-y.oudjana@protonmail.com> In-Reply-To: From: Dmitry Baryshkov Date: Sat, 16 Oct 2021 18:09:43 +0300 Message-ID: Subject: Re: [PATCH 7/8] arm64: dts: qcom: msm8996: Add MSM8996 Pro support To: Yassine Oudjana Cc: Konrad Dybcio , Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Ilia Lin , Viresh Kumar , Nishanth Menon , "Rafael J. Wysocki" , Loic Poulain , AngeloGioacchino Del Regno , "open list:DRM DRIVER FOR MSM ADRENO GPU" , "open list:COMMON CLK FRAMEWORK" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , open list , Linux PM , ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: phone-devel@vger.kernel.org On Sat, 16 Oct 2021 at 17:51, Yassine Oudjana wrote: > > > On Fri, Oct 15 2021 at 23:01:54 +0400, Konrad Dybcio > wrote: > > > > On 14.10.2021 10:32, Yassine Oudjana wrote: > >> Add a new DTSI for MSM8996 Pro (MSM8996SG) with msm-id and CPU/GPU > >> OPPs. > >> CBF OPPs and CPR parameters will be added to it as well once > >> support for > >> CBF scaling and CPR is introduced. > >> > >> Signed-off-by: Yassine Oudjana > >> --- > >> arch/arm64/boot/dts/qcom/msm8996.dtsi | 82 +++---- > >> arch/arm64/boot/dts/qcom/msm8996pro.dtsi | 281 > >> +++++++++++++++++++++++ > >> 2 files changed, 322 insertions(+), 41 deletions(-) > >> create mode 100644 arch/arm64/boot/dts/qcom/msm8996pro.dtsi > >> > >> diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi > >> b/arch/arm64/boot/dts/qcom/msm8996.dtsi > >> index 94a846c3f1ee..5b2600a4fb2a 100644 > >> --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi > >> +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi > >> @@ -142,82 +142,82 @@ cluster0_opp: opp_table0 { > >> /* Nominal fmax for now */ > >> opp-307200000 { > >> opp-hz = /bits/ 64 <307200000>; > >> - opp-supported-hw = <0x77>; > >> + opp-supported-hw = <0x7>; > > > > You didn't describe what's the reason for changing this everywhere. > > > > If it's been always broken, perhaps make it a separate commit > > describing > > > > the issue. > > > > > > Konrad > > > > Before removing reading msm-id in qcom_cpufreq_nvmem, bits 0-2 (0x07) > were MSM8996 speed bins, while bits 4-6 (0x70) were MSM8996 Pro speed > bins. Now, only bits 0-2 are used for either one, so basically I moved > bits 4-6 into msm8996pro.dtsi after shifting them right to become bits > 0-2. > > I'll put this in a separate patch and describe the change. Could you please describe in the commit message why is it changed? IOW, what prompted you to split 8996SG support from main msm8996.dtsi? -- With best wishes Dmitry