From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.5 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2646CC433E6 for ; Tue, 9 Feb 2021 13:20:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C7EFF64EF3 for ; Tue, 9 Feb 2021 13:20:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231210AbhBINUh (ORCPT ); Tue, 9 Feb 2021 08:20:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54656 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230465AbhBINUf (ORCPT ); Tue, 9 Feb 2021 08:20:35 -0500 Received: from relay06.th.seeweb.it (relay06.th.seeweb.it [IPv6:2001:4b7a:2000:18::167]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6D774C061786 for ; Tue, 9 Feb 2021 05:19:39 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (unknown [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by m-r2.th.seeweb.it (Postfix) with ESMTPSA id 708C03EEB8; Tue, 9 Feb 2021 14:19:37 +0100 (CET) Subject: Re: [PATCH v2 07/11] clk: qcom: mmcc-msm8998: Set CLK_GET_RATE_NOCACHE to pixel/byte clks To: Stephen Boyd , linux-arm-msm@vger.kernel.org Cc: konrad.dybcio@somainline.org, marijn.suijten@somainline.org, martin.botka@somainline.org, phone-devel@vger.kernel.org, linux-kernel@vger.kernel.org, agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, robh+dt@kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org References: <20210114221059.483390-1-angelogioacchino.delregno@somainline.org> <20210114221059.483390-8-angelogioacchino.delregno@somainline.org> <161280847912.76967.9613917615673032246@swboyd.mtv.corp.google.com> From: AngeloGioacchino Del Regno Message-ID: Date: Tue, 9 Feb 2021 14:19:37 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.7.0 MIME-Version: 1.0 In-Reply-To: <161280847912.76967.9613917615673032246@swboyd.mtv.corp.google.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: phone-devel@vger.kernel.org Il 08/02/21 19:21, Stephen Boyd ha scritto: > Quoting AngeloGioacchino Del Regno (2021-01-14 14:10:55) >> The pixel and byte clocks rate should not be cached, as a VCO shutdown >> may clear the frequency setup and this may not be set again due to the >> cached rate being present. >> This will also be useful when shadow clocks will be implemented in >> the DSI PLL for seamless timing/resolution switch. >> >> Signed-off-by: AngeloGioacchino Del Regno >> --- >> drivers/clk/qcom/mmcc-msm8998.c | 8 ++++---- >> 1 file changed, 4 insertions(+), 4 deletions(-) > > We didn't do this on sdm845, so I'm not going to apply this patch. The > rate caching thing is a problem with the display driver that should be > fixed some other way vs. setting nocache here. > Ok, I agree.