From: "David E. Box" <david.e.box@linux.intel.com>
To: irenic.rajneesh@gmail.com, david.e.box@linux.intel.com,
hdegoede@redhat.com, mgross@linux.intel.com,
gayatri.kammela@intel.com
Cc: platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH V2 4/9] platform/x86: intel_pmc_core: Show LPM residency in microseconds
Date: Fri, 16 Apr 2021 20:12:47 -0700 [thread overview]
Message-ID: <20210417031252.3020837-5-david.e.box@linux.intel.com> (raw)
In-Reply-To: <20210417031252.3020837-1-david.e.box@linux.intel.com>
From: Gayatri Kammela <gayatri.kammela@intel.com>
Modify the low power mode (LPM or sub-state) residency counters to display
in microseconds just like the slp_s0_residency counter. The granularity of
the counter is approximately 30.5us per tick. Double this value then divide
by two to maintain accuracy.
Signed-off-by: Gayatri Kammela <gayatri.kammela@intel.com>
Signed-off-by: David E. Box <david.e.box@linux.intel.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Rajneesh Bhardwaj <irenic.rajneesh@gmail.com>
---
V2: No change
drivers/platform/x86/intel_pmc_core.c | 14 ++++++++++++--
drivers/platform/x86/intel_pmc_core.h | 3 +++
2 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c
index c02f63c00ecc..0e59a84b51bf 100644
--- a/drivers/platform/x86/intel_pmc_core.c
+++ b/drivers/platform/x86/intel_pmc_core.c
@@ -580,6 +580,7 @@ static const struct pmc_reg_map tgl_reg_map = {
.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
.ltr_ignore_max = TGL_NUM_IP_IGN_ALLOWED,
.lpm_num_maps = TGL_LPM_NUM_MAPS,
+ .lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2,
.lpm_en_offset = TGL_LPM_EN_OFFSET,
.lpm_priority_offset = TGL_LPM_PRI_OFFSET,
.lpm_residency_offset = TGL_LPM_RESIDENCY_OFFSET,
@@ -1138,17 +1139,26 @@ static int pmc_core_ltr_show(struct seq_file *s, void *unused)
}
DEFINE_SHOW_ATTRIBUTE(pmc_core_ltr);
+static inline u64 adjust_lpm_residency(struct pmc_dev *pmcdev, u32 offset,
+ const int lpm_adj_x2)
+{
+ u64 lpm_res = pmc_core_reg_read(pmcdev, offset);
+
+ return GET_X2_COUNTER((u64)lpm_adj_x2 * lpm_res);
+}
+
static int pmc_core_substate_res_show(struct seq_file *s, void *unused)
{
struct pmc_dev *pmcdev = s->private;
+ const int lpm_adj_x2 = pmcdev->map->lpm_res_counter_step_x2;
u32 offset = pmcdev->map->lpm_residency_offset;
int i, mode;
seq_printf(s, "%-10s %-15s\n", "Substate", "Residency");
pmc_for_each_mode(i, mode, pmcdev) {
- seq_printf(s, "%-10s %-15u\n", pmc_lpm_modes[mode],
- pmc_core_reg_read(pmcdev, offset + (4 * mode)));
+ seq_printf(s, "%-10s %-15llu\n", pmc_lpm_modes[mode],
+ adjust_lpm_residency(pmcdev, offset + (4 * mode), lpm_adj_x2));
}
return 0;
diff --git a/drivers/platform/x86/intel_pmc_core.h b/drivers/platform/x86/intel_pmc_core.h
index 2ffe0eba36e1..aa44fd5399cc 100644
--- a/drivers/platform/x86/intel_pmc_core.h
+++ b/drivers/platform/x86/intel_pmc_core.h
@@ -188,9 +188,11 @@ enum ppfear_regs {
#define ICL_PMC_SLP_S0_RES_COUNTER_STEP 0x64
#define LPM_MAX_NUM_MODES 8
+#define GET_X2_COUNTER(v) ((v) >> 1)
#define TGL_NUM_IP_IGN_ALLOWED 22
#define TGL_PMC_SLP_S0_RES_COUNTER_STEP 0x7A
+#define TGL_PMC_LPM_RES_COUNTER_STEP_X2 61 /* 30.5us * 2 */
/*
* Tigerlake Power Management Controller register offsets
@@ -268,6 +270,7 @@ struct pmc_reg_map {
const u32 pm_vric1_offset;
/* Low Power Mode registers */
const int lpm_num_maps;
+ const int lpm_res_counter_step_x2;
const u32 lpm_en_offset;
const u32 lpm_priority_offset;
const u32 lpm_residency_offset;
--
2.25.1
next prev parent reply other threads:[~2021-04-17 3:12 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-17 3:12 [PATCH V2 0/9] intel_pmc_core: Add sub-state requirements and mode David E. Box
2021-04-17 3:12 ` [PATCH V2 1/9] platform/x86: intel_pmc_core: Don't use global pmcdev in quirks David E. Box
2021-04-17 3:12 ` [PATCH V2 2/9] platform/x86: intel_pmc_core: Remove global struct pmc_dev David E. Box
2021-04-17 3:12 ` [PATCH V2 3/9] platform/x86: intel_pmc_core: Handle sub-states generically David E. Box
2021-04-17 3:12 ` David E. Box [this message]
2021-04-17 3:12 ` [PATCH V2 5/9] platform/x86: intel_pmc_core: Get LPM requirements for Tiger Lake David E. Box
2021-04-17 5:55 ` kernel test robot
2021-04-17 6:25 ` kernel test robot
2021-04-17 8:52 ` Hans de Goede
2021-04-18 1:59 ` David E. Box
2021-04-17 9:00 ` Hans de Goede
2021-04-18 1:43 ` David E. Box
2021-04-17 3:12 ` [PATCH V2 6/9] platform/x86: intel_pmc_core: Add requirements file to debugfs David E. Box
2021-04-17 3:12 ` [PATCH V2 7/9] platform/x86: intel_pmc_core: Add option to set/clear LPM mode David E. Box
2021-04-17 3:12 ` [PATCH V2 8/9] platform/x86: intel_pmc_core: Add LTR registers for Tiger Lake David E. Box
2021-04-17 3:12 ` [PATCH V2 9/9] platform/x86: intel_pmc_core: Add support for Alder Lake PCH-P David E. Box
2021-04-17 9:12 ` [PATCH V2 0/9] intel_pmc_core: Add sub-state requirements and mode Hans de Goede
2021-04-19 8:47 ` Hans de Goede
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