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b=dOhKr4e+/ol2t4r7PUCdc6P16CQjomm5rgH5s8mEMf6g1yBTFeWSbw0cZ8T4hQH+gDzz0FW1zJblz7/TdHdeDYBMICX1vZQ21luh2Ztrt+tvdZhZuchdtH5T307VKm7bk+5vkWgkrnYl7Cy/5t/FV3cq7A5TrXXtB9MFfhGjYaE= Authentication-Results: amd.com; dkim=none (message not signed) header.d=none;amd.com; dmarc=none action=none header.from=amd.com; Received: from SA0PR12MB4510.namprd12.prod.outlook.com (2603:10b6:806:94::8) by SN6PR12MB2637.namprd12.prod.outlook.com (2603:10b6:805:6b::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4649.15; Wed, 3 Nov 2021 18:39:21 +0000 Received: from SA0PR12MB4510.namprd12.prod.outlook.com ([fe80::7cbc:2454:74b9:f4ea]) by SA0PR12MB4510.namprd12.prod.outlook.com ([fe80::7cbc:2454:74b9:f4ea%6]) with mapi id 15.20.4649.020; Wed, 3 Nov 2021 18:39:21 +0000 Message-ID: <54185145-cbec-319f-d450-a41b7f81d700@amd.com> Date: Wed, 3 Nov 2021 13:39:19 -0500 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.2.1 Subject: Re: [PATCH v5 3/3] platform/x86: amd-pmc: Add support for AMD Smart Trace Buffer Content-Language: en-US To: Sanket Goswami , Shyam-sundar.S-k@amd.com, hdegoede@redhat.com, mgross@linux.intel.com Cc: platform-driver-x86@vger.kernel.org References: <20211029172304.2998-1-Sanket.Goswami@amd.com> <20211029172304.2998-4-Sanket.Goswami@amd.com> From: "Limonciello, Mario" In-Reply-To: <20211029172304.2998-4-Sanket.Goswami@amd.com> Content-Type: text/plain; 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This nonintrusive way is always running in the > background and trace is stored into the SoC. > > This patch provides mechanism to access the STB buffer using the read > and write routines. > > Co-developed-by: Shyam Sundar S K > Signed-off-by: Shyam Sundar S K > Signed-off-by: Sanket Goswami > Tested-by: Scott Bruce > --- > Changes in v5: > - Use kfree() only once in .open as suggested by Hans. > > Changes in v4: > - Use kzalloc() for memory allocation. > > Changes in v3: > - Use sizeof(u32) with multiplier as suggested by Mark Gross. > > Changes in v2: > - Create amd_pmc_stb_debugfs_fops structure to get STB data. > - Address review comments from Hans. > > drivers/platform/x86/amd-pmc.c | 127 +++++++++++++++++++++++++++++++++ > 1 file changed, 127 insertions(+) > > diff --git a/drivers/platform/x86/amd-pmc.c b/drivers/platform/x86/amd-pmc.c > index ea099f7759f2..a39354ea96c4 100644 > --- a/drivers/platform/x86/amd-pmc.c > +++ b/drivers/platform/x86/amd-pmc.c > @@ -35,6 +35,12 @@ > #define AMD_PMC_SCRATCH_REG_CZN 0x94 > #define AMD_PMC_SCRATCH_REG_YC 0xD14 > > +/* STB Registers */ > +#define AMD_PMC_STB_INDEX_ADDRESS 0xF8 > +#define AMD_PMC_STB_INDEX_DATA 0xFC > +#define AMD_PMC_STB_PMI_0 0x03E30600 > +#define AMD_PMC_STB_PREDEF 0xC6000001 > + > /* Base address of SMU for mapping physical address to virtual address */ > #define AMD_PMC_SMU_INDEX_ADDRESS 0xB8 > #define AMD_PMC_SMU_INDEX_DATA 0xBC > @@ -82,6 +88,7 @@ > #define SOC_SUBSYSTEM_IP_MAX 12 > #define DELAY_MIN_US 2000 > #define DELAY_MAX_US 3000 > +#define FIFO_SIZE 4096 > enum amd_pmc_def { > MSG_TEST = 0x01, > MSG_OS_HINT_PCO, > @@ -128,8 +135,14 @@ struct amd_pmc_dev { > #endif /* CONFIG_DEBUG_FS */ > }; > > +static bool enable_stb; > +module_param(enable_stb, bool, 0644); > +MODULE_PARM_DESC(enable_stb, "Enable the STB debug mechanism"); > + > static struct amd_pmc_dev pmc; > static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret); > +static int amd_pmc_write_stb(struct amd_pmc_dev *dev, u32 data); > +static int amd_pmc_read_stb(struct amd_pmc_dev *dev, u32 *buf); > > static inline u32 amd_pmc_reg_read(struct amd_pmc_dev *dev, int reg_offset) > { > @@ -176,6 +189,50 @@ static int amd_pmc_get_smu_version(struct amd_pmc_dev *dev) > return 0; > } > > +static int amd_pmc_stb_debugfs_open(struct inode *inode, struct file *filp) > +{ > + struct amd_pmc_dev *dev = filp->f_inode->i_private; > + u32 size = FIFO_SIZE * sizeof(u32); > + u32 *buf; > + int rc; > + > + buf = kzalloc(size, GFP_KERNEL); > + if (!buf) > + return -ENOMEM; > + > + rc = amd_pmc_read_stb(dev, buf); > + if (rc) { > + kfree(buf); > + return rc; > + } > + > + filp->private_data = buf; > + return rc; > +} > + > +static ssize_t amd_pmc_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, > + loff_t *pos) > +{ > + if (!filp->private_data) > + return -EINVAL; > + > + return simple_read_from_buffer(buf, size, pos, filp->private_data, > + FIFO_SIZE * sizeof(u32)); > +} > + > +static int amd_pmc_stb_debugfs_release(struct inode *inode, struct file *filp) > +{ > + kfree(filp->private_data); > + return 0; > +} > + > +const struct file_operations amd_pmc_stb_debugfs_fops = { > + .owner = THIS_MODULE, > + .open = amd_pmc_stb_debugfs_open, > + .read = amd_pmc_stb_debugfs_read, > + .release = amd_pmc_stb_debugfs_release, > +}; > + > static int amd_pmc_idlemask_read(struct amd_pmc_dev *pdev, struct device *dev, > struct seq_file *s) > { > @@ -289,6 +346,10 @@ static void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev) > &s0ix_stats_fops); > debugfs_create_file("amd_pmc_idlemask", 0644, dev->dbgfs_dir, dev, > &amd_pmc_idlemask_fops); > + /* Enable STB only when the module_param is set */ > + if (enable_stb) > + debugfs_create_file("stb_read", 0644, dev->dbgfs_dir, dev, > + &amd_pmc_stb_debugfs_fops); Have you considered using debugfs_create_blob instead? Wouldn't this make it match the data type more closely? > } > #else > static inline void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev) > @@ -485,6 +546,9 @@ static int __maybe_unused amd_pmc_suspend(struct device *dev) > if (rc) > dev_err(pdev->dev, "suspend failed\n"); > > + if (enable_stb) > + amd_pmc_write_stb(pdev, AMD_PMC_STB_PREDEF); > + > return rc; > } > > @@ -505,6 +569,10 @@ static int __maybe_unused amd_pmc_resume(struct device *dev) > /* Dump the IdleMask to see the blockers */ > amd_pmc_idlemask_read(pdev, dev, NULL); > > + /* Write data incremented by 1 to distinguish in stb_read */ > + if (enable_stb) > + amd_pmc_write_stb(pdev, AMD_PMC_STB_PREDEF + 1); > + > return 0; > } > > @@ -521,6 +589,65 @@ static const struct pci_device_id pmc_pci_ids[] = { > { } > }; > > +static int amd_pmc_write_stb(struct amd_pmc_dev *dev, u32 data) > +{ > + int err; > + > + err = pci_write_config_dword(dev->rdev, AMD_PMC_STB_INDEX_ADDRESS, AMD_PMC_STB_PMI_0); > + if (err) { > + dev_err(dev->dev, "failed to write addr in stb: 0x%X\n", > + AMD_PMC_STB_INDEX_ADDRESS); > + err = pcibios_err_to_errno(err); > + goto err_pci_dev_put; > + } > + > + err = pci_write_config_dword(dev->rdev, AMD_PMC_STB_INDEX_DATA, data); > + if (err) { > + dev_err(dev->dev, "failed to write data in stb: 0x%X\n", > + AMD_PMC_STB_INDEX_DATA); > + err = pcibios_err_to_errno(err); > + goto err_pci_dev_put; > + } > + > + return 0; > + > +err_pci_dev_put: > + pci_dev_put(dev->rdev); > + return err; > +} > + > +static int amd_pmc_read_stb(struct amd_pmc_dev *dev, u32 *buf) > +{ > + int i, err; > + u32 value; > + > + err = pci_write_config_dword(dev->rdev, AMD_PMC_STB_INDEX_ADDRESS, AMD_PMC_STB_PMI_0); > + if (err) { > + dev_err(dev->dev, "error writing addr to stb: 0x%X\n", > + AMD_PMC_STB_INDEX_ADDRESS); > + err = pcibios_err_to_errno(err); > + goto err_pci_dev_put; > + } > + > + for (i = 0; i < FIFO_SIZE; i++) { > + err = pci_read_config_dword(dev->rdev, AMD_PMC_STB_INDEX_DATA, &value); > + if (err) { > + dev_err(dev->dev, "error reading data from stb: 0x%X\n", > + AMD_PMC_STB_INDEX_DATA); > + err = pcibios_err_to_errno(err); > + goto err_pci_dev_put; > + } > + > + *buf++ = value; > + } > + > + return 0; > + > +err_pci_dev_put: > + pci_dev_put(dev->rdev); > + return err; > +} > + > static int amd_pmc_probe(struct platform_device *pdev) > { > struct amd_pmc_dev *dev = &pmc; >