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[2001:1c00:c1e:bf00:1054:9d19:e0f0:8214]) by smtp.gmail.com with ESMTPSA id ho19sm12440376ejc.57.2021.04.07.07.48.17 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 07 Apr 2021 07:48:17 -0700 (PDT) Subject: Re: [PATCH 8/9] platform/x86: intel_pmc_core: Add LTR registers for Tiger Lake To: "David E. Box" , irenic.rajneesh@gmail.com, mgross@linux.intel.com, gayatri.kammela@intel.com Cc: platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org References: <20210401030558.2301621-1-david.e.box@linux.intel.com> <20210401030558.2301621-9-david.e.box@linux.intel.com> From: Hans de Goede Message-ID: Date: Wed, 7 Apr 2021 16:48:16 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.7.0 MIME-Version: 1.0 In-Reply-To: <20210401030558.2301621-9-david.e.box@linux.intel.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: platform-driver-x86@vger.kernel.org Hi, On 4/1/21 5:05 AM, David E. Box wrote: > From: Gayatri Kammela > > Just like Ice Lake, Tiger Lake uses Cannon Lake's LTR information > and supports a few additional registers. Hence add the LTR registers > specific to Tiger Lake to the cnp_ltr_show_map[]. > > Also adjust the number of LTR IPs for Tiger Lake to the correct amount. > > Signed-off-by: Gayatri Kammela > Signed-off-by: David E. Box Thanks, patch looks good to me: Reviewed-by: Hans de Goede Regards, Hans > --- > drivers/platform/x86/intel_pmc_core.c | 2 ++ > drivers/platform/x86/intel_pmc_core.h | 4 +++- > 2 files changed, 5 insertions(+), 1 deletion(-) > > diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c > index 458c0056e7a1..9168062c927e 100644 > --- a/drivers/platform/x86/intel_pmc_core.c > +++ b/drivers/platform/x86/intel_pmc_core.c > @@ -383,6 +383,8 @@ static const struct pmc_bit_map cnp_ltr_show_map[] = { > * a list of core SoCs using this. > */ > {"WIGIG", ICL_PMC_LTR_WIGIG}, > + {"THC0", TGL_PMC_LTR_THC0}, > + {"THC1", TGL_PMC_LTR_THC1}, > /* Below two cannot be used for LTR_IGNORE */ > {"CURRENT_PLATFORM", CNP_PMC_LTR_CUR_PLT}, > {"AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT}, > diff --git a/drivers/platform/x86/intel_pmc_core.h b/drivers/platform/x86/intel_pmc_core.h > index f41f61aa7008..634130b589a2 100644 > --- a/drivers/platform/x86/intel_pmc_core.h > +++ b/drivers/platform/x86/intel_pmc_core.h > @@ -192,8 +192,10 @@ enum ppfear_regs { > #define ETR3_CLEAR_LPM_EVENTS_BIT 28 > #define LPM_STS_LATCH_MODE_BIT 31 > > -#define TGL_NUM_IP_IGN_ALLOWED 22 > #define TGL_PMC_SLP_S0_RES_COUNTER_STEP 0x7A > +#define TGL_PMC_LTR_THC0 0x1C04 > +#define TGL_PMC_LTR_THC1 0x1C08 > +#define TGL_NUM_IP_IGN_ALLOWED 23 > #define TGL_PMC_LPM_RES_COUNTER_STEP_X2 61 /* 30.5us * 2 */ > > /* >