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[2001:1c00:c32:7800:5bfa:a036:83f0:f9ec]) by smtp.gmail.com with ESMTPSA id r24-20020a50d698000000b004af71e8cc3dsm3584347edi.60.2023.03.16.02.59.39 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 16 Mar 2023 02:59:40 -0700 (PDT) Message-ID: Date: Thu, 16 Mar 2023 10:59:39 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.1 Subject: Re: [PATCH v3 6/8] platform/x86/intel/ifs: Implement Array BIST test Content-Language: en-US, nl To: "Joseph, Jithu" , markgross@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, gregkh@linuxfoundation.org, rostedt@goodmis.org, ashok.raj@intel.com, tony.luck@intel.com, linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, patches@lists.linux.dev, ravi.v.shankar@intel.com, thiago.macieira@intel.com, athenas.jimenez.gonzalez@intel.com, sohil.mehta@intel.com References: <20230214234426.344960-1-jithu.joseph@intel.com> <20230301015942.462799-1-jithu.joseph@intel.com> <20230301015942.462799-7-jithu.joseph@intel.com> <628e092c-793e-96ce-71f5-80392ad69569@redhat.com> <9dde72aa-a28d-2b0e-7b90-6b1996dbf202@intel.com> From: Hans de Goede In-Reply-To: <9dde72aa-a28d-2b0e-7b90-6b1996dbf202@intel.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: platform-driver-x86@vger.kernel.org Hi, On 3/13/23 17:37, Joseph, Jithu wrote: > Hans, > > Thank-you very much for the review. > > On 3/13/2023 9:24 AM, Hans de Goede wrote: > > >>> >>> +#define SPINUNIT 100 /* 100 nsec */ >>> +static atomic_t array_cpus_out; >> >> This variable is only inc-ed + read, it is never reset to 0 >> so the "while (atomic_read(t) < all_cpus)" >> check only works for the first test run. >> > > It is reset to zero as annotated below. Let me know if this doesn't address your concern. Ah, I somehow missed that despite looking for it twice, yes that is fine. >> Also even static atomic_t variables must be initialized, you cannot >> assume that using using zeroed mem is a valid value for an atomic_t. >> >> And this is also shared between all smt pairs, so if 2 "real" >> CPU cores with both 2 sibblings are asked to run IFS tests at >> the same time, then array_cpus_out will get increased 4 times >> in total, breaking the wait_for_sibbling loop as soon as >> the counter reaches 2, so before the tests are done. > > Only one IFS test is allowed at a time. This is done using "ifs_sem" defined in sysfs.c Ah I see. After taking a closer look I do see one unrelated issue with this patch sysfs.c: run_test_store() does: if (!ifsd->loaded) rc = -EPERM; else rc = do_core_test(cpu, dev); But AFAICT the loaded check really only applies to the first (intel_ifs_0 device) test type and the Array BIST test should work fine when loaded is false. So I think that the if (!ifsd->loaded) error check should be moved to ifs_test_core() ? Regards, Hans > > ... > >>> +static void ifs_array_test_core(int cpu, struct device *dev) >>> +{ >>> + union ifs_array command = {}; >>> + bool timed_out = false; >>> + struct ifs_data *ifsd; >>> + unsigned long timeout; >>> + >>> + ifsd = ifs_get_data(dev); >>> + >>> + command.array_bitmask = ~0U; >>> + timeout = jiffies + HZ / 2; >>> + >>> + do { >>> + if (time_after(jiffies, timeout)) { >>> + timed_out = true; >>> + break; >>> + } >>> + atomic_set(&array_cpus_out, 0); > > The above line is where the zero initialization happens before every test. > >>> + stop_core_cpuslocked(cpu, do_array_test, &command); >>> + >>> + if (command.ctrl_result) >>> + break; >>> + } while (command.array_bitmask); >>> + >>> + ifsd->scan_details = command.data; >>> + >>> + if (command.ctrl_result) >>> + ifsd->status = SCAN_TEST_FAIL; >>> + else if (timed_out || command.array_bitmask) >>> + ifsd->status = SCAN_NOT_TESTED; >>> + else >>> + ifsd->status = SCAN_TEST_PASS; >>> +} > > Jithu >