From: Richard Henderson <richard.henderson@linaro.org>
To: Luis Fernando Fujita Pires <luis.pires@eldorado.org.br>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Cc: Matheus Kowalczuk Ferst <matheus.ferst@eldorado.org.br>,
"qemu-ppc@nongnu.org" <qemu-ppc@nongnu.org>,
Bruno Piazera Larsen <bruno.larsen@eldorado.org.br>
Subject: Re: [PATCH 1/1] decodetree: Add support for 64-bit instructions
Date: Wed, 7 Apr 2021 08:18:09 -0700 [thread overview]
Message-ID: <0054264c-3cf8-5e53-e29f-97dd7db47406@linaro.org> (raw)
In-Reply-To: <CP2PR80MB36688C896376D6D8601E1EB5DA759@CP2PR80MB3668.lamprd80.prod.outlook.com>
On 4/7/21 7:59 AM, Luis Fernando Fujita Pires wrote:
> Allow '64' to be specified for the instruction width command line params
> and use the appropriate insn/field data types, mask, extract and deposit
> functions in that case.
>
> This will be used to implement the new 64-bit Power ISA 3.1 instructions.
>
> Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
> ---
> docs/devel/decodetree.rst | 3 ---
> scripts/decodetree.py | 25 ++++++++++++++++++++-----
> 2 files changed, 20 insertions(+), 8 deletions(-)
Looks good.
> --- a/docs/devel/decodetree.rst
> +++ b/docs/devel/decodetree.rst
> @@ -40,9 +40,6 @@ and returns an integral value extracted from there.
>
> A field with no ``unnamed_fields`` and no ``!function`` is in error.
>
> -FIXME: the fields of the structure into which this result will be stored
> -is restricted to ``int``. Which means that we cannot expand 64-bit items.
Let's replace this FIXME with a sentence or two documenting the type used.
r~
prev parent reply other threads:[~2021-04-07 15:19 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-07 14:59 [PATCH 1/1] decodetree: Add support for 64-bit instructions Luis Fernando Fujita Pires
2021-04-07 15:18 ` Richard Henderson [this message]
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