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[83.57.174.129]) by smtp.gmail.com with ESMTPSA id p10sm20997816wrx.2.2019.10.22.10.36.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 22 Oct 2019 10:36:27 -0700 (PDT) Subject: Re: [PATCH 3/5] aspeed: Add a DRAM memory region at the SoC level To: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= , Peter Maydell References: <20191016085035.12136-1-clg@kaod.org> <20191016085035.12136-4-clg@kaod.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <01328c05-0f16-c53c-19b1-825d3b910dcf@redhat.com> Date: Tue, 22 Oct 2019 19:36:26 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.1.1 MIME-Version: 1.0 In-Reply-To: <20191016085035.12136-4-clg@kaod.org> Content-Language: en-US X-MC-Unique: g4MmtLDDOMWFmiDgcBG9og-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jae Hyun Yoo , Andrew Jeffery , Eddie James , qemu-devel@nongnu.org, qemu-arm@nongnu.org, Joel Stanley Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 10/16/19 10:50 AM, C=C3=A9dric Le Goater wrote: > Currently, we link the DRAM memory region to the FMC model (for DMAs) > through a property alias at the SoC level. The I2C model will need a > similar region for DMA support, add a DRAM region property at the SoC > level for both model to use. >=20 > Signed-off-by: C=C3=A9dric Le Goater > --- > include/hw/arm/aspeed_soc.h | 1 + > hw/arm/aspeed_ast2600.c | 7 +++++-- > hw/arm/aspeed_soc.c | 9 +++++++-- > 3 files changed, 13 insertions(+), 4 deletions(-) >=20 > diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h > index cccb684a19bb..3375ef91607f 100644 > --- a/include/hw/arm/aspeed_soc.h > +++ b/include/hw/arm/aspeed_soc.h > @@ -40,6 +40,7 @@ typedef struct AspeedSoCState { > ARMCPU cpu[ASPEED_CPUS_NUM]; > uint32_t num_cpus; > A15MPPrivState a7mpcore; > + MemoryRegion *dram_mr; > MemoryRegion sram; > AspeedVICState vic; > AspeedRtcState rtc; > diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c > index 931887ac681f..a403c2aae067 100644 > --- a/hw/arm/aspeed_ast2600.c > +++ b/hw/arm/aspeed_ast2600.c > @@ -158,8 +158,6 @@ static void aspeed_soc_ast2600_init(Object *obj) > typename); > object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs", > &error_abort); > - object_property_add_alias(obj, "dram", OBJECT(&s->fmc), "dram", > - &error_abort); > =20 > for (i =3D 0; i < sc->spis_num; i++) { > snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, = socname); > @@ -362,6 +360,11 @@ static void aspeed_soc_ast2600_realize(DeviceState *= dev, Error **errp) > } > =20 > /* FMC, The number of CS is set at the board level */ > + object_property_set_link(OBJECT(&s->fmc), OBJECT(s->dram_mr), "dram"= , &err); > + if (err) { > + error_propagate(errp, err); > + return; > + } > object_property_set_int(OBJECT(&s->fmc), sc->memmap[ASPEED_SDRAM], > "sdram-base", &err); > if (err) { > diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c > index f4fe243458fd..dd1ee0e3336d 100644 > --- a/hw/arm/aspeed_soc.c > +++ b/hw/arm/aspeed_soc.c > @@ -175,8 +175,6 @@ static void aspeed_soc_init(Object *obj) > typename); > object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs", > &error_abort); > - object_property_add_alias(obj, "dram", OBJECT(&s->fmc), "dram", > - &error_abort); > =20 > for (i =3D 0; i < sc->spis_num; i++) { > snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, = socname); > @@ -323,6 +321,11 @@ static void aspeed_soc_realize(DeviceState *dev, Err= or **errp) > aspeed_soc_get_irq(s, ASPEED_I2C)); > =20 > /* FMC, The number of CS is set at the board level */ > + object_property_set_link(OBJECT(&s->fmc), OBJECT(s->dram_mr), "dram"= , &err); > + if (err) { > + error_propagate(errp, err); > + return; > + } > object_property_set_int(OBJECT(&s->fmc), sc->memmap[ASPEED_SDRAM], > "sdram-base", &err); > if (err) { > @@ -429,6 +432,8 @@ static void aspeed_soc_realize(DeviceState *dev, Erro= r **errp) > } > static Property aspeed_soc_properties[] =3D { > DEFINE_PROP_UINT32("num-cpus", AspeedSoCState, num_cpus, 0), > + DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION= , > + MemoryRegion *), > DEFINE_PROP_END_OF_LIST(), > }; > =20 >=20 Reviewed-by: Philippe Mathieu-Daud=C3=A9