From: Richard Henderson <richard.henderson@linaro.org>
To: Alistair Francis <alistair.francis@wdc.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair23@gmail.com, bmeng.cn@gmail.com, palmer@dabbelt.com
Subject: Re: [PATCH v2 3/5] target/riscv: Fix 32-bit HS mode access permissions
Date: Fri, 2 Apr 2021 10:14:23 -0700 [thread overview]
Message-ID: <05fb06ef-6a2e-e2a5-1972-52970b03ee76@linaro.org> (raw)
In-Reply-To: <cb1ef2061547dc9028ce3cf4f6622588f9c09149.1617290165.git.alistair.francis@wdc.com>
On 4/1/21 8:17 AM, Alistair Francis wrote:
> Signed-off-by: Alistair Francis<alistair.francis@wdc.com>
> ---
> target/riscv/csr.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2021-04-02 17:16 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-01 15:17 [PATCH v2 0/5] RISC-V: Convert the CSR access functions to use Alistair Francis
2021-04-01 15:17 ` [PATCH v2 1/5] target/riscv: Convert the RISC-V exceptions to an enum Alistair Francis
2021-04-02 17:11 ` Richard Henderson
2021-04-01 15:17 ` [PATCH v2 2/5] target/riscv: Use the RISCVException enum for CSR predicates Alistair Francis
2021-04-02 17:14 ` Richard Henderson
2021-04-06 8:34 ` Bin Meng
2021-04-01 15:17 ` [PATCH v2 3/5] target/riscv: Fix 32-bit HS mode access permissions Alistair Francis
2021-04-02 17:14 ` Richard Henderson [this message]
2021-04-06 8:34 ` Bin Meng
2021-04-01 15:17 ` [PATCH v2 4/5] target/riscv: Use the RISCVException enum for CSR operations Alistair Francis
2021-04-02 17:17 ` Richard Henderson
2021-04-06 8:34 ` Bin Meng
2021-04-01 15:18 ` [PATCH v2 5/5] target/riscv: Use RISCVException enum for CSR access Alistair Francis
2021-04-02 17:18 ` Richard Henderson
2021-04-06 8:34 ` Bin Meng
2021-04-07 13:55 ` [PATCH v2 0/5] RISC-V: Convert the CSR access functions to use Alistair Francis
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