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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id g19sm11679128pfh.134.2020.02.15.19.41.52 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 15 Feb 2020 19:41:52 -0800 (PST) Subject: Re: [PATCH v3 1/2] target/arm: Support SError injection To: Gavin Shan , qemu-devel@nongnu.org, qemu-arm@nongnu.org References: <20200214055950.62477-1-gshan@redhat.com> <20200214055950.62477-2-gshan@redhat.com> From: Richard Henderson Message-ID: <0c00d0d4-19c5-0802-8fd3-f583bb270709@linaro.org> Date: Sat, 15 Feb 2020 19:41:50 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: <20200214055950.62477-2-gshan@redhat.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, drjones@redhat.com, jthierry@redhat.com, aik@ozlabs.ru, maz@kernel.org, eric.auger@redhat.com, shan.gavin@gmail.com, pbonzini@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 2/13/20 9:59 PM, Gavin Shan wrote: > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index b0762a76c4..180e29fb83 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -78,7 +78,7 @@ static bool arm_cpu_has_work(CPUState *cs) > && cs->interrupt_request & > (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD > | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ > - | CPU_INTERRUPT_EXITTB); > + | ARM_CPU_SERROR | CPU_INTERRUPT_EXITTB); CPU_INTERRUPT_SERROR, not ARM_CPU_SERROR. > @@ -570,6 +573,16 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) > goto found; > } > } > + > + if (interrupt_request & CPU_INTERRUPT_SERROR) { > + excp_idx = EXCP_SERROR; > + target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); > + if (arm_excp_unmasked(cs, excp_idx, target_el, > + cur_el, secure, hcr_el2)) { > + goto found; > + } > + } > + > return false; > > found: If you're intending to use Serror for NMI, perhaps it should be the first bit tested, not the last. Otherwise some bug that leaves a normal hard interrupt line high will keep delivering the interrupt, and not the Serror. As the comment at the top of the function says, the priority is implementation defined, so we can put it anywhere we like. > @@ -594,13 +607,26 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) > * (which depends on state like BASEPRI, FAULTMASK and the > * currently active exception). > */ > - if (interrupt_request & CPU_INTERRUPT_HARD > - && (armv7m_nvic_can_take_pending_exception(env->nvic))) { > - cs->exception_index = EXCP_IRQ; > - cc->do_interrupt(cs); > - ret = true; > + if (!armv7m_nvic_can_take_pending_exception(env->nvic)) { > + return false; > + } > + > + if (interrupt_request & CPU_INTERRUPT_HARD) { > + excp_idx = EXCP_IRQ; > + goto found; > } > - return ret; > + > + if (interrupt_request & CPU_INTERRUPT_SERROR) { > + excp_idx = EXCP_SERROR; > + goto found; > + } Likewise. > - qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); > + qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 5); > } else { > - qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); > + qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 5); I wonder if we should have an ARM_CPU_NUM_IRQ define so that this is more automatic. > @@ -98,10 +100,11 @@ enum { > #endif > > /* Meanings of the ARMCPU object's four inbound GPIO lines */ > -#define ARM_CPU_IRQ 0 > -#define ARM_CPU_FIQ 1 > -#define ARM_CPU_VIRQ 2 > -#define ARM_CPU_VFIQ 3 > +#define ARM_CPU_IRQ 0 > +#define ARM_CPU_FIQ 1 > +#define ARM_CPU_VIRQ 2 > +#define ARM_CPU_VFIQ 3 > +#define ARM_CPU_SERROR 4 Comment is now wrong about the count. r~