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[88.21.202.17]) by smtp.gmail.com with ESMTPSA id s8sm2699999wrt.69.2020.05.14.00.59.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 14 May 2020 00:59:32 -0700 (PDT) Subject: Re: [PATCH v6 18/20] hw/block/nvme: factor out pmr setup To: Klaus Jensen , qemu-block@nongnu.org References: <20200514044611.734782-1-its@irrelevant.dk> <20200514044611.734782-19-its@irrelevant.dk> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <0c528722-0117-4842-cb5c-d37090ac71f2@redhat.com> Date: Thu, 14 May 2020 09:59:30 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.5.0 MIME-Version: 1.0 In-Reply-To: <20200514044611.734782-19-its@irrelevant.dk> Content-Language: en-US X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=205.139.110.120; envelope-from=philmd@redhat.com; helo=us-smtp-1.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/13 22:25:42 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Keith Busch , Javier Gonzalez , Maxim Levitsky Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 5/14/20 6:46 AM, Klaus Jensen wrote: > From: Klaus Jensen > > Signed-off-by: Klaus Jensen > Reviewed-by: Maxim Levitsky > --- > hw/block/nvme.c | 95 ++++++++++++++++++++++++++----------------------- > 1 file changed, 51 insertions(+), 44 deletions(-) > > diff --git a/hw/block/nvme.c b/hw/block/nvme.c > index d71a5f142d51..7254b66ae199 100644 > --- a/hw/block/nvme.c > +++ b/hw/block/nvme.c > @@ -58,6 +58,7 @@ > #define NVME_REG_SIZE 0x1000 > #define NVME_DB_SIZE 4 > #define NVME_CMB_BIR 2 > +#define NVME_PMR_BIR 2 > > #define NVME_GUEST_ERR(trace, fmt, ...) \ > do { \ > @@ -1463,6 +1464,55 @@ static void nvme_init_cmb(NvmeCtrl *n, PCIDevice *pci_dev) > PCI_BASE_ADDRESS_MEM_PREFETCH, &n->ctrl_mem); > } > > +static void nvme_init_pmr(NvmeCtrl *n, PCIDevice *pci_dev) > +{ > + /* Controller Capabilities register */ > + NVME_CAP_SET_PMRS(n->bar.cap, 1); > + > + /* PMR Capabities register */ > + n->bar.pmrcap = 0; > + NVME_PMRCAP_SET_RDS(n->bar.pmrcap, 0); > + NVME_PMRCAP_SET_WDS(n->bar.pmrcap, 0); > + NVME_PMRCAP_SET_BIR(n->bar.pmrcap, NVME_PMR_BIR); > + NVME_PMRCAP_SET_PMRTU(n->bar.pmrcap, 0); > + /* Turn on bit 1 support */ > + NVME_PMRCAP_SET_PMRWBM(n->bar.pmrcap, 0x02); > + NVME_PMRCAP_SET_PMRTO(n->bar.pmrcap, 0); > + NVME_PMRCAP_SET_CMSS(n->bar.pmrcap, 0); > + > + /* PMR Control register */ > + n->bar.pmrctl = 0; > + NVME_PMRCTL_SET_EN(n->bar.pmrctl, 0); > + > + /* PMR Status register */ > + n->bar.pmrsts = 0; > + NVME_PMRSTS_SET_ERR(n->bar.pmrsts, 0); > + NVME_PMRSTS_SET_NRDY(n->bar.pmrsts, 0); > + NVME_PMRSTS_SET_HSTS(n->bar.pmrsts, 0); > + NVME_PMRSTS_SET_CBAI(n->bar.pmrsts, 0); > + > + /* PMR Elasticity Buffer Size register */ > + n->bar.pmrebs = 0; > + NVME_PMREBS_SET_PMRSZU(n->bar.pmrebs, 0); > + NVME_PMREBS_SET_RBB(n->bar.pmrebs, 0); > + NVME_PMREBS_SET_PMRWBZ(n->bar.pmrebs, 0); > + > + /* PMR Sustained Write Throughput register */ > + n->bar.pmrswtp = 0; > + NVME_PMRSWTP_SET_PMRSWTU(n->bar.pmrswtp, 0); > + NVME_PMRSWTP_SET_PMRSWTV(n->bar.pmrswtp, 0); > + > + /* PMR Memory Space Control register */ > + n->bar.pmrmsc = 0; > + NVME_PMRMSC_SET_CMSE(n->bar.pmrmsc, 0); > + NVME_PMRMSC_SET_CBA(n->bar.pmrmsc, 0); > + > + pci_register_bar(pci_dev, NVME_PMRCAP_BIR(n->bar.pmrcap), > + PCI_BASE_ADDRESS_SPACE_MEMORY | > + PCI_BASE_ADDRESS_MEM_TYPE_64 | > + PCI_BASE_ADDRESS_MEM_PREFETCH, &n->pmrdev->mr); > +} > + > static void nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev) > { > uint8_t *pci_conf = pci_dev->config; > @@ -1541,50 +1591,7 @@ static void nvme_realize(PCIDevice *pci_dev, Error **errp) > if (n->params.cmb_size_mb) { > nvme_init_cmb(n, pci_dev); > } else if (n->pmrdev) { > - /* Controller Capabilities register */ > - NVME_CAP_SET_PMRS(n->bar.cap, 1); > - > - /* PMR Capabities register */ > - n->bar.pmrcap = 0; > - NVME_PMRCAP_SET_RDS(n->bar.pmrcap, 0); > - NVME_PMRCAP_SET_WDS(n->bar.pmrcap, 0); > - NVME_PMRCAP_SET_BIR(n->bar.pmrcap, 2); > - NVME_PMRCAP_SET_PMRTU(n->bar.pmrcap, 0); > - /* Turn on bit 1 support */ > - NVME_PMRCAP_SET_PMRWBM(n->bar.pmrcap, 0x02); > - NVME_PMRCAP_SET_PMRTO(n->bar.pmrcap, 0); > - NVME_PMRCAP_SET_CMSS(n->bar.pmrcap, 0); > - > - /* PMR Control register */ > - n->bar.pmrctl = 0; > - NVME_PMRCTL_SET_EN(n->bar.pmrctl, 0); > - > - /* PMR Status register */ > - n->bar.pmrsts = 0; > - NVME_PMRSTS_SET_ERR(n->bar.pmrsts, 0); > - NVME_PMRSTS_SET_NRDY(n->bar.pmrsts, 0); > - NVME_PMRSTS_SET_HSTS(n->bar.pmrsts, 0); > - NVME_PMRSTS_SET_CBAI(n->bar.pmrsts, 0); > - > - /* PMR Elasticity Buffer Size register */ > - n->bar.pmrebs = 0; > - NVME_PMREBS_SET_PMRSZU(n->bar.pmrebs, 0); > - NVME_PMREBS_SET_RBB(n->bar.pmrebs, 0); > - NVME_PMREBS_SET_PMRWBZ(n->bar.pmrebs, 0); > - > - /* PMR Sustained Write Throughput register */ > - n->bar.pmrswtp = 0; > - NVME_PMRSWTP_SET_PMRSWTU(n->bar.pmrswtp, 0); > - NVME_PMRSWTP_SET_PMRSWTV(n->bar.pmrswtp, 0); > - > - /* PMR Memory Space Control register */ > - n->bar.pmrmsc = 0; > - NVME_PMRMSC_SET_CMSE(n->bar.pmrmsc, 0); > - NVME_PMRMSC_SET_CBA(n->bar.pmrmsc, 0); > - > - pci_register_bar(pci_dev, NVME_PMRCAP_BIR(n->bar.pmrcap), > - PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64 | > - PCI_BASE_ADDRESS_MEM_PREFETCH, &n->pmrdev->mr); > + nvme_init_pmr(n, pci_dev); > } > > for (i = 0; i < n->num_namespaces; i++) { > Reviewed-by: Philippe Mathieu-Daudé