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([2a02:c7f:a69:1700:8897:9507:94c2:b98d]) by smtp.gmail.com with ESMTPSA id c65sm17187995wma.44.2019.08.18.01.10.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 18 Aug 2019 01:10:03 -0700 (PDT) To: Aleksandar Markovic , "Paul A. Clarke" References: <1565983669-6886-1-git-send-email-pc@us.ibm.com> From: Richard Henderson Openpgp: preference=signencrypt Message-ID: <0cfddc22-92ef-3067-9275-8f4f22ca9805@linaro.org> Date: Sun, 18 Aug 2019 09:10:01 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: Re: [Qemu-devel] [PATCH] ppc: Three floating point fixes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 8/16/19 11:59 PM, Aleksandar Markovic wrote: >> From: "Paul A. Clarke" ... >> ISA 3.0B has xscvdpspn leaving its result in word 1 of the target > register, >> and mffprwz expecting its input to come from word 0 of the source > register. >> This sequence fails with QEMU, as a shift is required between those two >> instructions. However, the hardware splats the result to both word 0 > and >> word 1 of its output register, so the shift is not necessary. >> Expect a future revision of the ISA to specify this behavior. >> > > Hmmm... Isn't this a gcc bug (using undocumented hardware feature), given > everything you said here? The key here is "expect a future revision of the ISA to specify this behavior". It's clearly within IBM's purview to adjust the specification to document a previously undocumented hardware feature. r~