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From: Richard Henderson <richard.henderson@linaro.org>
To: Alistair Francis <alistair23@gmail.com>,
	Alexey Baturo <baturo.alexey@gmail.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>,
	Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	space.monkey.delivers@gmail.com,
	Alistair Francis <Alistair.Francis@wdc.com>,
	kupokupokupopo@gmail.com, Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH v6 0/6] RISC-V Pointer Masking implementation
Date: Mon, 26 Oct 2020 12:10:21 -0700	[thread overview]
Message-ID: <0dd4b7ce-a894-6913-9a9e-d5775c62b13d@linaro.org> (raw)
In-Reply-To: <CAKmqyKO1AdNOynNLDBFR0=x3mbcRn4No_iw7DA8anGOnPwmwVw@mail.gmail.com>

On 10/23/20 5:25 PM, Alistair Francis wrote:
> On Thu, Oct 22, 2020 at 1:04 AM Alexey Baturo <baturo.alexey@gmail.com> wrote:
>>
>> Hi,
>>
>> Added missing sign-off on the first patch.
>>
>> Thanks
>>
>> Alexey Baturo (5):
>>   [RISCV_PM] Add J-extension into RISC-V
>>   [RISCV_PM] Support CSRs required for RISC-V PM extension except for
>>     ones in hypervisor mode
>>   [RISCV_PM] Print new PM CSRs in QEMU logs
>>   [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of
>>     instructions
>>   [RISCV_PM] Allow experimental J-ext to be turned on
>>
>> Anatoly Parshintsev (1):
>>   [RISCV_PM] Implement address masking functions required for RISC-V
>>     Pointer Masking extension
> 
> Thanks for the patches!
> 
> I don't know a lot about the J-extension, so it will take me some time
> to read into it before I can review this.
> 
> Maybe you can convince Richard to review it for you :P

Richard did review v3.  Alexey seems to have misplaced or not added the r-b
tags.  Although I missed that it misses the mask for the special hypervisor
load/store insns?


r~


      reply	other threads:[~2020-10-26 19:17 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-22  8:04 [PATCH v6 0/6] RISC-V Pointer Masking implementation Alexey Baturo
2020-10-22  8:04 ` [PATCH v6 1/6] [RISCV_PM] Add J-extension into RISC-V Alexey Baturo
2020-10-24  0:24   ` Alistair Francis
2020-10-22  8:04 ` [PATCH v6 2/6] [RISCV_PM] Support CSRs required for RISC-V PM extension except for ones in hypervisor mode Alexey Baturo
2020-10-22  8:04 ` [PATCH v6 3/6] [RISCV_PM] Print new PM CSRs in QEMU logs Alexey Baturo
2020-10-22  8:04 ` [PATCH v6 4/6] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions Alexey Baturo
2020-10-22  8:04 ` [PATCH v6 5/6] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension Alexey Baturo
2020-10-22  8:04 ` [PATCH v6 6/6] [RISCV_PM] Allow experimental J-ext to be turned on Alexey Baturo
2020-10-24  0:25 ` [PATCH v6 0/6] RISC-V Pointer Masking implementation Alistair Francis
2020-10-26 19:10   ` Richard Henderson [this message]

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