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Thu, 30 Jul 2020 11:26:23 +0000 (UTC) Message-ID: <10e041ac12802972dc4b093cb139c71cb92c108b.camel@redhat.com> Subject: Re: [PATCH v4 1/2] nvme: indicate CMB support through controller capabilities register From: Maxim Levitsky To: Klaus Jensen Date: Thu, 30 Jul 2020 14:26:22 +0300 In-Reply-To: <20200707191559.GA669353@apples.localdomain> References: <20200701214858.28515-1-andrzej.jakowski@linux.intel.com> <20200701214858.28515-2-andrzej.jakowski@linux.intel.com> <20200707191559.GA669353@apples.localdomain> User-Agent: Evolution 3.36.3 (3.36.3-1.fc32) MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=207.211.31.81; envelope-from=mlevitsk@redhat.com; helo=us-smtp-delivery-1.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/07/30 03:51:24 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kwolf@redhat.com, qemu-block@nongnu.org, Klaus Jensen , qemu-devel@nongnu.org, mreitz@redhat.com, Andrzej Jakowski , kbusch@kernel.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Tue, 2020-07-07 at 21:15 +0200, Klaus Jensen wrote: > On Jul 7 19:27, Maxim Levitsky wrote: > > On Wed, 2020-07-01 at 14:48 -0700, Andrzej Jakowski wrote: > > > This patch sets CMBS bit in controller capabilities register when user > > > configures NVMe driver with CMB support, so capabilites are correctly > > > reported to guest OS. > > > > > > Signed-off-by: Andrzej Jakowski > > > Reviewed-by: Klaus Jensen > > > --- > > > hw/block/nvme.c | 2 +- > > > include/block/nvme.h | 6 +++++- > > > 2 files changed, 6 insertions(+), 2 deletions(-) > > > > > > diff --git a/hw/block/nvme.c b/hw/block/nvme.c > > > index 1aee042d4c..9f11f3e9da 100644 > > > --- a/hw/block/nvme.c > > > +++ b/hw/block/nvme.c > > > @@ -1582,6 +1582,7 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pci_dev) > > > NVME_CAP_SET_TO(n->bar.cap, 0xf); > > > NVME_CAP_SET_CSS(n->bar.cap, 1); > > > NVME_CAP_SET_MPSMAX(n->bar.cap, 4); > > > + NVME_CAP_SET_CMBS(n->bar.cap, n->params.cmb_size_mb ? 1 : 0); > > > > > > n->bar.vs = 0x00010200; > > > n->bar.intmc = n->bar.intms = 0; > > > @@ -1591,7 +1592,6 @@ static void nvme_realize(PCIDevice *pci_dev, Error **errp) > > > { > > > NvmeCtrl *n = NVME(pci_dev); > > > Error *local_err = NULL; > > > - > > > int i; > > > > > > nvme_check_constraints(n, &local_err); > > > diff --git a/include/block/nvme.h b/include/block/nvme.h > > > index 1720ee1d51..14cf398dfa 100644 > > > --- a/include/block/nvme.h > > > +++ b/include/block/nvme.h > > > @@ -35,6 +35,7 @@ enum NvmeCapShift { > > > CAP_MPSMIN_SHIFT = 48, > > > CAP_MPSMAX_SHIFT = 52, > > > CAP_PMR_SHIFT = 56, > > > + CAP_CMB_SHIFT = 57, > > > }; > > > > > > enum NvmeCapMask { > > > @@ -48,6 +49,7 @@ enum NvmeCapMask { > > > CAP_MPSMIN_MASK = 0xf, > > > CAP_MPSMAX_MASK = 0xf, > > > CAP_PMR_MASK = 0x1, > > > + CAP_CMB_MASK = 0x1, > > > }; > > > > > > #define NVME_CAP_MQES(cap) (((cap) >> CAP_MQES_SHIFT) & CAP_MQES_MASK) > > > @@ -78,8 +80,10 @@ enum NvmeCapMask { > > > << CAP_MPSMIN_SHIFT) > > > #define NVME_CAP_SET_MPSMAX(cap, val) (cap |= (uint64_t)(val & CAP_MPSMAX_MASK)\ > > > << CAP_MPSMAX_SHIFT) > > > -#define NVME_CAP_SET_PMRS(cap, val) (cap |= (uint64_t)(val & CAP_PMR_MASK)\ > > > +#define NVME_CAP_SET_PMRS(cap, val) (cap |= (uint64_t)(val & CAP_PMR_MASK) \ > > > << CAP_PMR_SHIFT) > > > +#define NVME_CAP_SET_CMBS(cap, val) (cap |= (uint64_t)(val & CAP_CMB_MASK) \ > > > + << CAP_CMB_SHIFT) > > > > > > enum NvmeCcShift { > > > CC_EN_SHIFT = 0, > > > > I wonder how this could have beeing forgotten. Hmm. > > I see that Linux kernel uses CMBSZ != for that. > > I guess this explains it. > > > > Reviewed-by: Maxim Levitsky > > > > It is a v1.4 field. The CMB support was added when NVMe was at v1.2. > And the Linux kernel is also basically adhering to v1.3 wrt. CMB > support. In v1.4 the host actually needs to specifically enable the CMB > - and that is not something the kernel does currently IIRC. > Ah, makes sense! I by now have specs for each NVME revision, but I am getting lazy sometimes to cross-check them. Best regards, Maxim Levitsky