From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60204) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZD71v-0001Lu-Rv for qemu-devel@nongnu.org; Thu, 09 Jul 2015 04:18:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZD71q-0002GG-JH for qemu-devel@nongnu.org; Thu, 09 Jul 2015 04:18:03 -0400 Received: from mail-oi0-x232.google.com ([2607:f8b0:4003:c06::232]:33347) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZD71q-0002G6-Bg for qemu-devel@nongnu.org; Thu, 09 Jul 2015 04:17:58 -0400 Received: by oiyy130 with SMTP id y130so184360887oiy.0 for ; Thu, 09 Jul 2015 01:17:58 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Thu, 9 Jul 2015 09:17:21 +0100 Message-Id: <1436429849-18052-7-git-send-email-rth@twiddle.net> In-Reply-To: <1436429849-18052-1-git-send-email-rth@twiddle.net> References: <1436429849-18052-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 06/14] target-i386: Perform set/reset_inhibit_irq inline List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, ehabkost@redhat.com With helpers that can be reused for other things. Signed-off-by: Richard Henderson --- target-i386/cc_helper.c | 10 ---------- target-i386/helper.h | 2 -- target-i386/translate.c | 37 ++++++++++++++++++++++++++++--------- 3 files changed, 28 insertions(+), 21 deletions(-) diff --git a/target-i386/cc_helper.c b/target-i386/cc_helper.c index ecbf0ec..1bf89aa 100644 --- a/target-i386/cc_helper.c +++ b/target-i386/cc_helper.c @@ -382,13 +382,3 @@ void helper_sti_vm(CPUX86State *env) } } #endif - -void helper_set_inhibit_irq(CPUX86State *env) -{ - env->hflags |= HF_INHIBIT_IRQ_MASK; -} - -void helper_reset_inhibit_irq(CPUX86State *env) -{ - env->hflags &= ~HF_INHIBIT_IRQ_MASK; -} diff --git a/target-i386/helper.h b/target-i386/helper.h index e6df35c..0c957bf 100644 --- a/target-i386/helper.h +++ b/target-i386/helper.h @@ -61,8 +61,6 @@ DEF_HELPER_1(cli, void, env) DEF_HELPER_1(sti, void, env) DEF_HELPER_1(clac, void, env) DEF_HELPER_1(stac, void, env) -DEF_HELPER_1(set_inhibit_irq, void, env) -DEF_HELPER_1(reset_inhibit_irq, void, env) DEF_HELPER_3(boundw, void, env, tl, int) DEF_HELPER_3(boundl, void, env, tl, int) DEF_HELPER_1(rsm, void, env) diff --git a/target-i386/translate.c b/target-i386/translate.c index eb30401..9303dc0 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -2393,14 +2393,36 @@ static void gen_debug(DisasContext *s, target_ulong cur_eip) s->is_jmp = DISAS_TB_JUMP; } +static void gen_set_hflag(DisasContext *s, uint32_t mask) +{ + if ((s->flags & mask) == 0) { + TCGv_i32 t = tcg_temp_new_i32(); + tcg_gen_ld_i32(t, cpu_env, offsetof(CPUX86State, hflags)); + tcg_gen_ori_i32(t, t, mask); + tcg_gen_st_i32(t, cpu_env, offsetof(CPUX86State, hflags)); + tcg_temp_free_i32(t); + s->flags |= mask; + } +} + +static void gen_reset_hflag(DisasContext *s, uint32_t mask) +{ + if (s->flags & mask) { + TCGv_i32 t = tcg_temp_new_i32(); + tcg_gen_ld_i32(t, cpu_env, offsetof(CPUX86State, hflags)); + tcg_gen_andi_i32(t, t, ~mask); + tcg_gen_st_i32(t, cpu_env, offsetof(CPUX86State, hflags)); + tcg_temp_free_i32(t); + s->flags &= ~mask; + } +} + /* generate a generic end of block. Trace exception is also generated if needed */ static void gen_eob(DisasContext *s) { gen_update_cc_op(s); - if (s->tb->flags & HF_INHIBIT_IRQ_MASK) { - gen_helper_reset_inhibit_irq(cpu_env); - } + gen_reset_hflag(s, HF_INHIBIT_IRQ_MASK); if (s->tb->flags & HF_RF_MASK) { gen_helper_reset_rf(cpu_env); } @@ -5190,8 +5212,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, /* if reg == SS, inhibit interrupts/trace. */ /* If several instructions disable interrupts, only the _first_ does it */ - if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK)) - gen_helper_set_inhibit_irq(cpu_env); + gen_set_hflag(s, HF_INHIBIT_IRQ_MASK); s->tf = 0; } if (s->is_jmp) { @@ -5258,8 +5279,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, /* if reg == SS, inhibit interrupts/trace */ /* If several instructions disable interrupts, only the _first_ does it */ - if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK)) - gen_helper_set_inhibit_irq(cpu_env); + gen_set_hflag(s, HF_INHIBIT_IRQ_MASK); s->tf = 0; } if (s->is_jmp) { @@ -6813,8 +6833,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, /* interruptions are enabled only the first insn after sti */ /* If several instructions disable interrupts, only the _first_ does it */ - if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK)) - gen_helper_set_inhibit_irq(cpu_env); + gen_set_hflag(s, HF_INHIBIT_IRQ_MASK); /* give a chance to handle pending irqs */ gen_jmp_im(s->pc - s->cs_base); gen_eob(s); -- 2.4.3