From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49638) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aK6Eb-00082O-HN for qemu-devel@nongnu.org; Fri, 15 Jan 2016 10:24:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aK6Ea-0000wX-D8 for qemu-devel@nongnu.org; Fri, 15 Jan 2016 10:24:17 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:59462) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aK6Ea-0000u7-5a for qemu-devel@nongnu.org; Fri, 15 Jan 2016 10:24:16 -0500 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1aK6EP-00016c-VA for qemu-devel@nongnu.org; Fri, 15 Jan 2016 15:24:05 +0000 From: Peter Maydell Date: Fri, 15 Jan 2016 15:23:55 +0000 Message-Id: <1452871445-4221-2-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1452871445-4221-1-git-send-email-peter.maydell@linaro.org> References: <1452871445-4221-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 01/11] target-arm: Use the right MMU index in arm_regime_using_lpae_format List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org From: Alvise Rigo arm_regime_using_lpae_format checks whether the LPAE extension is used for stage 1 translation regimes. MMU indexes not exclusively of a stage 1 regime won't work with this method. In case of ARMMMUIdx_S12NSE0 or ARMMMUIdx_S12NSE1, offset these values by ARMMMUIdx_S1NSE0 to get the right index indicating a stage 1 translation regime. Rename also the function to arm_s1_regime_using_lpae_format and update the comments to reflect the change. Signed-off-by: Alvise Rigo Message-id: 1452854262-19550-1-git-send-email-a.rigo@virtualopensystems.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target-arm/helper.c | 12 ++++++++---- target-arm/internals.h | 5 +++-- target-arm/op_helper.c | 2 +- 3 files changed, 12 insertions(+), 7 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 59d5a41..faeaaa8 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -5996,11 +5996,15 @@ static inline bool regime_using_lpae_format(CPUARMState *env, return false; } -/* Returns true if the translation regime is using LPAE format page tables. - * Used when raising alignment exceptions, whose FSR changes depending on - * whether the long or short descriptor format is in use. */ -bool arm_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) +/* Returns true if the stage 1 translation regime is using LPAE format page + * tables. Used when raising alignment exceptions, whose FSR changes depending + * on whether the long or short descriptor format is in use. */ +bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) { + if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) { + mmu_idx += ARMMMUIdx_S1NSE0; + } + return regime_using_lpae_format(env, mmu_idx); } diff --git a/target-arm/internals.h b/target-arm/internals.h index b925aaa..d226bbe 100644 --- a/target-arm/internals.h +++ b/target-arm/internals.h @@ -441,8 +441,9 @@ struct ARMMMUFaultInfo { bool arm_tlb_fill(CPUState *cpu, vaddr address, int rw, int mmu_idx, uint32_t *fsr, ARMMMUFaultInfo *fi); -/* Return true if the translation regime is using LPAE format page tables */ -bool arm_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx); +/* Return true if the stage 1 translation regime is using LPAE format page + * tables */ +bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx); /* Raise a data fault alignment exception for the specified virtual address */ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, int is_write, diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index e42d287..951fc5a 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -149,7 +149,7 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, int is_write, /* the DFSR for an alignment fault depends on whether we're using * the LPAE long descriptor format, or the short descriptor format */ - if (arm_regime_using_lpae_format(env, cpu_mmu_index(env, false))) { + if (arm_s1_regime_using_lpae_format(env, cpu_mmu_index(env, false))) { env->exception.fsr = 0x21; } else { env->exception.fsr = 0x1; -- 1.9.1