From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46397) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aT5j4-000713-02 for qemu-devel@nongnu.org; Tue, 09 Feb 2016 05:40:56 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aT5j2-0005Tx-Ur for qemu-devel@nongnu.org; Tue, 09 Feb 2016 05:40:53 -0500 Received: from mail-pa0-x241.google.com ([2607:f8b0:400e:c03::241]:32768) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aT5j2-0005Tt-KX for qemu-devel@nongnu.org; Tue, 09 Feb 2016 05:40:52 -0500 Received: by mail-pa0-x241.google.com with SMTP id gc2so114276pab.0 for ; Tue, 09 Feb 2016 02:40:52 -0800 (PST) Sender: Richard Henderson From: Richard Henderson Date: Tue, 9 Feb 2016 21:40:03 +1100 Message-Id: <1455014403-10742-16-git-send-email-rth@twiddle.net> In-Reply-To: <1455014403-10742-1-git-send-email-rth@twiddle.net> References: <1455014403-10742-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 15/15] tcg-mips: Use mipsr6 instructions in calls List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: james.hogan@imgtec.com, aurelien@aurel32.net Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c | 30 ++++++++++++++++++------------ 1 file changed, 18 insertions(+), 12 deletions(-) diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c index 06e15d4..1b876af 100644 --- a/tcg/mips/tcg-target.c +++ b/tcg/mips/tcg-target.c @@ -357,7 +357,9 @@ typedef enum { OPC_SH = 051 << 26, OPC_SW = 053 << 26, OPC_BC = 062 << 26, + OPC_JIC = 066 << 26, OPC_LD = 067 << 26, + OPC_JIALC = 076 << 26, OPC_SD = 077 << 26, OPC_SPECIAL = 000 << 26, @@ -1313,28 +1315,30 @@ static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret, } } -static void tcg_out_call_int(TCGContext *s, tcg_insn_unit *arg, bool tail) +static void tcg_out_call_int(TCGContext *s, tcg_insn_unit *arg, + bool tail, bool delay) { /* Note that the ABI requires the called function's address to be loaded into T9, even if a direct branch is in range. */ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg); /* But do try a direct branch, allowing the cpu better insn prefetch. */ - if (tail) { - if (!tcg_out_opc_jmp(s, OPC_J, arg)) { - tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_T9, 0); - } + if (tcg_out_opc_jmp(s, tail ? OPC_J : OPC_JAL, arg)) { + if (!delay) { + tcg_out_nop(s); + } + } else if (use_mips32r6_instructions && !delay) { + tcg_out_opc_reg(s, tail ? OPC_JIC : OPC_JIALC, 0, TCG_REG_T9, 0); + } else if (tail) { + tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_T9, 0); } else { - if (!tcg_out_opc_jmp(s, OPC_JAL, arg)) { - tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0); - } + tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0); } } static void tcg_out_call(TCGContext *s, tcg_insn_unit *arg) { - tcg_out_call_int(s, arg, false); - tcg_out_nop(s); + tcg_out_call_int(s, arg, false, false); } #if defined(CONFIG_SOFTMMU) @@ -1558,7 +1562,8 @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) } i = tcg_out_call_iarg_imm(s, i, oi); i = tcg_out_call_iarg_imm(s, i, (intptr_t)l->raddr); - tcg_out_call_int(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)], false); + tcg_out_call_int(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)], + false, true); /* delay slot */ tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0); @@ -1622,7 +1627,8 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) computation to take place in the return address register. */ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RA, (intptr_t)l->raddr); i = tcg_out_call_iarg_reg(s, i, TCG_REG_RA); - tcg_out_call_int(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)], true); + tcg_out_call_int(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)], + true, true); /* delay slot */ tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0); } -- 2.5.0