From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46127) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aT5iZ-0006In-TZ for qemu-devel@nongnu.org; Tue, 09 Feb 2016 05:40:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aT5iZ-0005O0-50 for qemu-devel@nongnu.org; Tue, 09 Feb 2016 05:40:23 -0500 Received: from mail-pa0-x243.google.com ([2607:f8b0:400e:c03::243]:33781) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aT5iY-0005NU-UE for qemu-devel@nongnu.org; Tue, 09 Feb 2016 05:40:23 -0500 Received: by mail-pa0-x243.google.com with SMTP id gc2so113789pab.0 for ; Tue, 09 Feb 2016 02:40:22 -0800 (PST) Sender: Richard Henderson From: Richard Henderson Date: Tue, 9 Feb 2016 21:39:52 +1100 Message-Id: <1455014403-10742-5-git-send-email-rth@twiddle.net> In-Reply-To: <1455014403-10742-1-git-send-email-rth@twiddle.net> References: <1455014403-10742-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 04/15] tcg-mips: Adjust load/store functions for mips64 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: james.hogan@imgtec.com, aurelien@aurel32.net Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c index 43210c5..8f90360 100644 --- a/tcg/mips/tcg-target.c +++ b/tcg/mips/tcg-target.c @@ -733,7 +733,7 @@ static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data, if (ofs != lo) { tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - lo); if (addr != TCG_REG_ZERO) { - tcg_out_opc_reg(s, OPC_ADDU, TCG_TMP0, TCG_TMP0, addr); + tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP0, TCG_TMP0, addr); } addr = TCG_TMP0; } @@ -743,13 +743,21 @@ static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data, static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1, intptr_t arg2) { - tcg_out_ldst(s, OPC_LW, arg, arg1, arg2); + MIPSInsn opc = OPC_LD; + if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { + opc = OPC_LW; + } + tcg_out_ldst(s, opc, arg, arg1, arg2); } static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1, intptr_t arg2) { - tcg_out_ldst(s, OPC_SW, arg, arg1, arg2); + MIPSInsn opc = OPC_SD; + if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { + opc = OPC_SW; + } + tcg_out_ldst(s, opc, arg, arg1, arg2); } static inline void tcg_out_addi(TCGContext *s, TCGReg reg, TCGArg val) -- 2.5.0